Pratap Reddy

Software Engineer

Bengaluru, Karnataka, India20 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in ASIC Physical Design with extensive experience.
Proficient in Cadence tools for layout verification.
Strong background in standard cell library development.

Stackforce AI infers this person is a highly skilled ASIC Physical Design Engineer with expertise in VLSI and semiconductor industries.

Contact

Skills

Core Skills

AsicPhysical DesignCadence VirtuosoIc Layout

Other Skills

FloorplanPlacementClock tree synthesisRoutingParasitic extractionECO and timing fixesPV Signoffcustom layoutstdcell layout designCustom/Semi custom PNR implementationQDSP core hard macrosPPA optimizationCadence EDA toolLayout DesignCalibre

About

Specialties:Physical Design (Well experienced in Floorplan, Placement, Clock tree synthesis, Routing, Parasitic extraction, ECO and timing fixes, PV Signoff, custom layout and stdcell layout design)

Experience

20 yrs 4 mos

Total Experience

4 yrs 8 mos

Average Tenure

1 yr 6 mos

Current Experience

Micron technology

Principal Engineer

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India

ASIC Physical design

ASICPhysical DesignFloorplanPlacementClock tree synthesisRouting+5

Qualcomm

2 roles

Staff physical design Engineer

Promoted

Dec 2012 – Dec 2024 · 12 yrs · Bengaluru, Karnataka, India

Custom/Semi custom PNR implementation for QDSP core hard macros and optimize the design to achieve better PPA

Custom/Semi custom PNR implementationQDSP core hard macrosPPA optimizationASICPhysical Design

Engineer

Dec 2006 – Jul 2010 · 3 yrs 7 mos · Bangalore

Standard Cell Layout Development:
Worked on Standard Cell library development for different technolgies such as 28nm,45nm,65nm,90nm based on different architectures.

Standard Cell Layout Development28nm45nm65nm90nmdifferent architectures+2

Ibm

Sr. R & D Engineer

Jul 2010 – Dec 2012 · 2 yrs 5 mos · Bangalore

Physical design using Cadence EDA tool respectively.
Various Physical Design and Development activity on Layout Design using Cadence Virtuoso.
Layout verification using Calibre, Hercules
Floor Planning, Placement ,Custom Clock Tree , Routing and Sign off checks
Layout Verification which consist of Design Rule Checks (DRC), Antenna Violations, Layout Versus Schematic (LVS), Density cleaning

Cadence EDA toolLayout DesignCalibreHerculesFloor PlanningPlacement+8