Ashutosh K. — Software Engineer
12+ Years of Experience in VLSI Design Verification: - Testbench planning & development from scratch - Reusing(integrate/seperate VIP/BFM, update scoreboard) existing testbench - Testplan development, coding & execution - Debug the test failures - Block level verification - IP level verification - SOC level verification - RTL simulation - GLS(Gate level simulation) - SVA(Assertion based verification) - CDV(Coverage driven verification) Specialties: - System Verilog - OOPs Concepts, Assertions, Functional Coverage - Methodologies - UVM - Processor concept - AMBA - AXI, AHB, APB - PCIe - MIPI MPHY
Stackforce AI infers this person is a VLSI Design Verification expert with extensive experience in ASIC and FPGA industries.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 4 mos
Career Highlights
- Over 12 years in VLSI Design Verification.
- Expert in System Verilog and UVM methodologies.
- Proficient in SOC and IP level verification.
Work Experience
Mobiveil Inc.
Senior Design Verification Engineer (1 yr 2 mos)
Broadcom Inc.
Verification Consultant (6 mos)
Qualcomm
Verification Consultant (6 mos)
ALTEN Calsoft Labs
Verification Engineer (1 yr 1 mo)
NXP Semiconductors
Verification Consultant (10 mos)
Sankalp Semiconductor
Senior Design Verification Engineer (1 yr 7 mos)
Micrel
Verification Consultant (8 mos)
VERIFxN
Project Engineer (2 yrs 6 mos)
Education
Engineer's Degree at Rajiv Gandhi Prodyogiki Vishwavidyalaya
High School at National Convent High School
at Jiwaji University
