Nithin Krishna M S — Director of Engineering

>> Technical: RTL2GDS: As a core Physical Design Engineer , implemented multiple critical designs from Synthesis of RTL , through physical design implementation and sign off checks till GDS tapeout on critical blocks and top level. Top Level Physical design work: on Mobile chips, IOT Chips, TestChip, Hierarchical Block's, DDR Phy Block level Physical design work from synthesis through complete place&route (Floorplan,Powerplan,placement,CTS,routing) to sign off check and closure (Physical Verification/timing/EM/IR) worked on Front End: Synthesis, Timing Constraints, Low Power constraints, LEC/FEV from rtl2netlist, Sanity check, Scan Insertion/Scan DRC, Good understand in insertion of DFT SCAN/MBIST with dft timing constraints ,Timing Closure ScriptingTcl Perl awk vim Python Tools Used: Industry standard Signoff's from Synopsys/Cadence/MentorGraphics Worked For: SOC's, IP's Technology: 5nm, 7nm, 14nm, 20nm, 45nm, 65nm, 90nm Multiple Foundry. Blocks complexities: Rectangle, Rectilinear, Hierarchical, Logic/Macro/IP Oriented, Challenging Closure of Timing/Congestion >> Managing Team: Managed Technically leading 20+ team member working each on multiple million instance count complex blocks on lower advanced technology nodes in short term critical tapeouts.

Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in physical design and team management.

Location: Bengaluru, Karnataka, India

Experience: 16 yrs 8 mos