Deepak Kathiresan

CTO

Bengaluru, Karnataka, India16 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

14+ years of experience in STA and Physical Design.
Expert in Timing closure for complex IPs and SoCs.
Proven leadership in mentoring and managing teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Static Timing Analysis and Physical Design.

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Skills

Core Skills

Static Timing AnalysisPhysical DesignSynthesis

Other Skills

Timing SignoffMethodology InitiativesMentoringCollaborationRTL to GDSIIConstraints DevelopmentTiming ClosureFormal Equivalence CheckBlock Level SynthesisConstraints ValidationLECSTACLPFormal VerificationLinting

About

- 14+ years of experience in STA, Constraints development, Synthesis, LEC and Physical Design on various tech. nodes (Intel: 18A, 3nm, 4nm, 7nm, 10nm, 14nm, 22nm, 28nm; TSMC: 28nm, 32nm & 45nm) - Experienced in Timing closure for complex IPs, including PCIe Gen6, CIO80 and for few SoCs. Leading methodology initiatives for the HSIO IPs. - Experienced in Synthesis and LEC for multiple SoC projects. - Experienced in Constraints development, validation for Synthesis as well as timing closure. - Hands-on experience in Physical design and Physical Verification. - Project planning, Execution and Tracking, Mentoring juniors and managing them. Specialties: STA, Constraints Development, Synthesis, LEC, Physical Design.

Experience

16 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

5 yrs 4 mos

Current Experience

Intel corporation

Technical Lead

Feb 2021 – Present · 5 yrs 4 mos · Bengaluru, Karnataka, India

Responsible for Timing Signoff of all global Hard-IPs including complex IPs like PCIE-4/5/6, CIO etc. across various tech nodes from 7nm to 18A.
Involved in Synthesis and Physical Design activities for the HIPs.
Involved in PPA push activity and methodology initiatives for the complex HSIO IPs.
Mentoring juniors and CWs in the team and delegating tasks to them.

Timing SignoffSynthesisPhysical DesignMethodology InitiativesMentoringStatic Timing Analysis

Altran

Technical Lead

Aug 2019 – Feb 2021 · 1 yr 6 mos · Chennai, Tamil Nadu, India · On-site

Ownership of Timing Signoff for different flavors of PLL IPs on different technology nodes at Intel.
Involved in Synthesis and Physical design activities for PLL IPs.
Collaborated closely with cross-functional teams, providing timely and actionable feedback to enhance design convergence and efficiency.
Mentoring and leading a small team of both Altran and Intel.

Timing SignoffSynthesisPhysical DesignCollaborationMentoringStatic Timing Analysis

Synapse design inc.

Technical Lead

May 2016 – Aug 2019 · 3 yrs 3 mos · Bengaluru Area, India

RTL~2~GDSII for 2 blocks @ Intel Labs. This includes complete ownership of RTL2GDSII for a complex low power block.
Responsibilities include Synthesis and Constraints development, Physical Design, Timing Signoff for MMMC, LEC Checks, Redhawk (Static, Dynamic) for IR Drop analysis, Spyglass & CLP for low power checks, Physical Verification (LVS/DRC Cleanup).
Timing Signoff for CBBs @ Intel Hard-IP team. Responsible for constraints/UPF development and timing closure of the CBBs for different IPs for MMMC and delivering .libs to the customers.
Managing few juniors and mentoring them in timing activities.

RTL to GDSIISynthesisConstraints DevelopmentPhysical DesignTiming SignoffStatic Timing Analysis

Intel corporation

Consultant

Aug 2014 – Apr 2016 · 1 yr 8 mos · Penang, Malaysia

Performed Synthesis and Constraints development at the block level.
Involved in Floorplan, Placement, CTS, Routing and Timing closure for the same blocks.
Complete ownership of Formal Equivalence check for 20 partitions.
Involved in full chip constraints development and timing closure across MMMC for 2 SoCs.

SynthesisConstraints DevelopmentTiming ClosureFormal Equivalence CheckStatic Timing AnalysisPhysical Design

Qualcomm

Consultant

Nov 2011 – May 2014 · 2 yrs 6 mos · Bangalore

Did block level synthesis for HMs with constraints validation. Cleaning up of Setup violations by using optimization techniques.
Involved in Synthesis/Constraints development/Pre-layout STA at the top level as well.
Performed LEC and CLP checks at the full chip level.

Block Level SynthesisConstraints ValidationLECSTAStatic Timing AnalysisSynthesis