utpal barman

Director of Engineering

Bengaluru, Karnataka, India24 yrs 10 mos experience

Highly Stable

Key Highlights

20+ years of experience in high-performance IP leadership.
Expert in PCIe design and productization.
Proven track record in project management and team development.

Stackforce AI infers this person is a seasoned expert in semiconductor design and architecture, specializing in high-speed IP development.

Contact

Skills

Other Skills

SoCASICFunctional VerificationRTL designStatic Timing AnalysisProject ManagementPCIeChip ArchitectureVerilogVLSITiming ClosureEmbedded SystemsLow-power Design

About

Seasoned professional with 20+ years of experience in leading and delivering high performance IP's. Hands on experience in leading/managing Architecture, design, verification for several high speed IP’s like PCIE express, memory controller, ethernet controllers. Contributed in designing and productizing multiple generation of PCIE express controller till Gen5. Support customer issues post productizing and provide solutions for successful product launches. Influence product roadmap discussions to define PCIE requirements, provide schedule/hiring projections, hire/building new teams. Excellent execution and project management skills delivering several generation of products on time. Technically coach new team members to bring the best out of them and be future leaders. Highly focused, self motivated, proactive and adaptive to industry changes. Excellent communication and interpersonal skill dealing with cross geo teams across HW, SW, product marketing, systems engineering etc.

Experience

24 yrs 10 mos

Total Experience

10 yrs 4 mos

Average Tenure

4 yrs 6 mos

Current Experience

Qualcomm

Director Of Engineering

Dec 2021 – Present · 4 yrs 6 mos

Nvidia

3 roles

Sr. Engineering Manager

Promoted

Oct 2012 – Dec 2021 · 9 yrs 2 mos

Project Lead

Jul 2010 – Oct 2012 · 2 yrs 3 mos

Lead PCIE IP design and verification for Gen3 Endpoint.
Project planning and execution.
Drive Chip POR decisions.

senior ASIC design engineer

Jan 2005 – Jan 2010 · 5 yrs

Worked on designing DDR2/3 memory controllers for several x86 based chipsets.
Lead team to architect, design, verify ground up DDR3 memory controller. Design was able to overclock 50% higher than state-of-the-art chipsets. Also worked on to define IO timing for this.
Hands on experience bringing up chips on multiple customer platforms. Coordinated with customers to resolve issues and help them take to production.
Partition timing, STA for full chip clocks and reset distribution.
Performance verification of GPU's.