Naveen Neelapala

CEO

Hyderabad, Telangana, India15 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and Semiconductor technologies.
Proven track record in device technology management.
Innovative solutions in virtual metrology and statistical modeling.

Stackforce AI infers this person is a Semiconductor Engineering expert with strong capabilities in VLSI and device technology.

Contact

Skills

Core Skills

VlsiTiming SignoffStatistical ModelingVirtual MetrologyVlsi Physical DesignSignal Integrity

Other Skills

RC extractionSTA toolsSkew modelingAOCV Transition characterizationMonte-Carlo Spice simulationsVirtual Metrology modelingCVDSPC vs FDC dataIterative Backward EliminationPartial Least Squares RegressionWafer pattern recognitionSupervised learning methodologySTA closureECODRC clean

Experience

15 yrs 6 mos

Total Experience

3 yrs 10 mos

Average Tenure

10 yrs 6 mos

Current Experience

Micron technology

3 roles

Senior Manager, Device Technology

Promoted

Nov 2023 – Present · 2 yrs 7 mos

Principal Engineer - Device

Promoted

Nov 2020 – Dec 2023 · 3 yrs 1 mo

Senior Engineer - Device

Dec 2015 – Nov 2020 · 4 yrs 11 mos

Mediatek inc.

VLSI Timing SignOff Engineer

Apr 2014 – Nov 2015 · 1 yr 7 mos · Singapore

Responsible for Flow development and support in RC extraction (Star RC) and STA (Prime Time) tools.
Also handled Skew modeling, AOCV Transition characterization (based on Monte-Carlo Spice simulations).

RC extractionSTA toolsSkew modelingAOCV Transition characterizationMonte-Carlo Spice simulationsVLSI+1

Tsmc

Statistical Modeling Engineer

Sep 2012 – Mar 2014 · 1 yr 6 mos · Taiwan

Virtual Metrology modeling for CVD - SPC vs FDC data. Work included developing novel modeling solution "Iterative Backward Elimination - Partial Least Squares Regression" for better prediction accuracy by reducing noise.
Deployment & support for wafer pattern recognition flow (built using supervised learning methodology) which is meant to identify specific defect patterns on wafers running in the Line without manual inetrvention .

Virtual Metrology modelingCVDSPC vs FDC dataIterative Backward EliminationPartial Least Squares RegressionWafer pattern recognition+3

Mindtree ltd.

VLSI Physical Design Engineer

Jul 2007 – Jun 2009 · 1 yr 11 mos · India

Responsibilities include STA closure, ECO, DRC clean and Signal Integrity checks for Texas Instruments (client) projects on ARM based subsystems in 65nm and 45nm node.
Familiar with Synopsys Prime Time & Prime Time Signal Integrity, Magma Blast Fusion, Perl & Tcl

STA closureECODRC cleanSignal Integrity checksSynopsys Prime TimePrime Time Signal Integrity+5