Rajasekhar R

Software Engineer

Bengaluru, Karnataka, India12 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI physical design from netlist to GDS2.
Successfully managed projects in advanced technology nodes.
Proficient in timing closure and physical verification.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in VLSI physical design and verification.

Contact

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

floorplanningplacementCTSroutingRC extractionphysical verificationVerilogICCSynopsys PrimetimePTSIModelSimXilinx ISEDCSTAR-RC extraction

About

having good experience in vlsi physical design from netlist to GDS2. successfully handled 28 nm, 20nm and 14nm projects ranging from thousands to multi million gate count. experienced in place&route , timing closer and physical verification at block level. specialties: DC, ICC,PT/SI, STAR-RC,calibre.

Experience

12 yrs 9 mos

Total Experience

6 yrs 4 mos

Average Tenure

8 yrs 3 mos

Current Experience

Qualcomm

3 roles

Senior Staff Engineer

Dec 2024 – Present · 1 yr 6 mos

Staff Engineer

Dec 2020 – Jan 2025 · 4 yrs 1 mo

Senior Lead Engineer

Feb 2018 – Nov 2020 · 2 yrs 9 mos

Amd

2 roles

Senior Design Engineer

Promoted

Jan 2017 – Jan 2018 · 1 yr

Design Enginner -2

Jun 2013 – Dec 2016 · 3 yrs 6 mos

working as physical design design engineer from netlist-GDS2 at blocks.
my primary responsibilities are block level floorplaning, placement,cts,routing,RC extraction timing closer and physical verification.

physical designfloorplanningplacementCTSroutingRC extraction+2