Dec 2023 – Jan 2025 · 1 yr 1 mo

• ● Working on building multiple blocks like Fault detection circuits, level shifters for a Point of Load (DC-DC Converter).
• ● Designed a HV LS which caters to high speed and no dc current consumption.
• ● Designed a low droop capless LDO which is low in power and area
• ● Working towards Building the LDO IP charter and working on realizing the old LDOs with
• PPA efficient LDOs for better revenue.
• ● Managing and working with a team of 2 junior engineers. Responsible for their ramp up and
• learning along with ensuring timely delivery of work

Oct 2020 – Dec 2023 · 3 yrs 2 mos

• ● Lead - BGR IP
• Responsible for end to end delivery of the IP including design, execution, reviews, cross
• functional validation (like HV, RV, BMODs, AMS) and final tape out in collaboration with the
• layout team
• Silicon debug and design enhancements for fixing bugs.
• ● DC DC Buck Converter Designer
• 1. Designed of a Pulse width Modulator in 3nm TSMC process
• 2. Designed of a Compensator in 7nm TSMC process
• Worked on top level Converter Controller action using voltage loop and current loop control for interaction of two chips which included ganging.
• ● Horizontal Activities
• 1. Worked on Analog-digital loops controlling trimming and offset cancellation using BMODs.
• 2. Found some errors in BMOD corresponding to the actual expected analog behavior.
• ● Post Silicon Activity
• Developing the testplan and interacting with the test engineers
• Worked on debugging the 3nm Silicon for PWM Generator designed
• Also worked on testing some top-level artefacts like power sequencing
• ● Top Level Activity
• Worked with the SOC team to get the inductor capacitor models and add it to the DC DC
• Converter behavioral model and test the loop for load conditions, stability, efficiency ● AMS Simulations
• Worked on AMS setup and validation for a switched capacitor based converter

Jun 2016 – Jul 2017 · 1 yr 1 mo · Hudson Massachusetts

• Working as an Analog Design Engineer on FIVR (Fully Integrated Voltage Regulator).
• Designed a reference generator circuit and level shifters. Also worked on solving HV/RV/Ageing issues in analog designs.
• Worked on designing the multiphase buck converter operation under different load conditions.

Jul 2017 – Oct 2020 · 3 yrs 3 mos · Bengaluru

• ● Positive LDO: Design of a positive programmable LDO operating from supply range of 4.5V-6V, sourcing 10mA Load with max upto 75mA, and Load Cap ranging between 2uF-10uF.
• ● Low Voltage Positive LDO: Design of a positive low voltage LDO with supply rangefrom 2V- 6.3V (switching supply as per power sequencing) sourcing 10mA Load and load cap ranging between 0.5uF-5uF.
• In the above two designs following sub blocks were designed in 130nm technology: 1. Error Amplifier
• 2. Trim Circuit
• 3. Programmable Reference Generator
• 4. Supply switching circuit
• 5. Soft Start Circuit
• ● Universal Supply Generator: Supply generator that generates a universal supplydepending
• on whichever supply is available.
• ● Chip Top Activities
• 1. Producing the trim/test document with respect to the register map for the TestEngineer
• 2. Generating the chiptop verilog netlist for Digital Verification
• 3. Building the chiptop schematic and measuring supply currents, along withgenerating the strategy for meeting the current requirements
• 4. Running Reliability, EM & HV Checks
• 5. Bench Testing and Validation
• 6. Testplan and Flow setup for Automatic Testing.
• 7. Post Silicon debug
• 8. Qualification of the chip
• ● DC-DC Converter
• 1. Design of a Zero Current Detector for a DC-DC Converter
• 2. Optimal selection of Inductor Capacitor Driver & Switch for a DC-DC Converter

Aug 2015 – May 2016 · 9 mos

• Teaching and helping students learn the Analog Circuits and designing
• Teaching Assistant for Analog Circuit Design (EEE433) under Dr. Sayfe Kiaei. - Spring 2016
• Help Students learn Analog & Digital Circuit design using Cadence.
• Teaching Assistant for Analog & Digital Circuits (EEE335) under Dr. Jeniffer Kitchen -Fall 2015

Aug 2015 – May 2016 · 9 mos

• Grading Homeworks, quizes, midterms and finals of a graduate level course in Analog Circuit Design (EEE433) under Dr. David Allee
• Grading Homeworks, quizes, midterms and finals of a graduate level course in Circuits II (EEE334) under Dr. David Allee

Aug 2015 – May 2016 · 9 mos

• Designing a Low Noise Nuclear Preamplifier. The idea is to design a small area low power CMOS based preamplifier for neutron detection.
• The study aims at establishing 100 preamps on a chip of size 1cm.
• Guide: Dr. David Allee

May 2015 – Aug 2015 · 3 mos · Dallas/Fort Worth Area

• Design/ Analysis and simulation of the following circuits with their verification for systematic and random offset.
• 1. Analog Circuit Designing at transistor level.
• 2. Design and exploring different current mirror topologies and optimizing for best headroom and minimum random variations.
• 3. Designing the layout of current mirror circuit using different layout topology. Comparing the pre and post layout results. Working with the number of fingers and multipliers to assimilate the best matching.
• 4. Design of a low power high headroom self biased folded cascode amplifier.
• 5. Design of a ramp and triangular wave generator and using the folded cascode as a comparator to generate a high frequency pulse.
• 6. Design and simulation of novel and new emerging schmitt trigger circuit.
• 7. Design & Simulation of a temperature sensor circuit using Bipolars.

Jul 2011 – Jul 2014 · 3 yrs · Gurgaon, India

• Developed Preliminary Conceptual layout & design of switchyards for transmission.
• Design/Sizing & Testing of power supplies, Battery banks, LT switchgears.
• Developed Physical & equipment layout designing.
• Transmission System Interconnection Cabling & Wiring system designing, calculation &
• routing.
• Soil Resistivity testing and ground grid design.
• SCADA, Communication through PLCC Designing and interfacing
• Reviewed and designed Protective Relay designing and relay programming using PLC ladder
• programming.
• Metering System Designing.
• Lightning protection & Illumination estimation for a switchyard layout..
• Preparing Cable Schedules

Jun 2010 – Aug 2010 · 2 mos · Dehradun,India

• Worked as an Intern designing a baseband modulation system.
• Work included:
• Simulink modeling/designing & Simulation results of Π/4 shifted DQPSK(linear baseband modulation scheme) Modulator-Demodulator for sample based over AWGN (Additive White Gausian Noise) Channel.RRC(raised Root cosine) Filter was used for pulse shaping.
• Baseband differential detector was used to filter out the various disturbances present.

Jun 2009 – Jul 2009 · 1 mo · Dehradun,India

• Worked on the laser technique being used in the Indian Military.
• Studied about the radar operated self protection machine used in Indian Military for protecting against the enemy.
• Studied and modeled the Tank designs and its aspects.