Parul Bahuguna — CEO
Experienced Application Specific Integrated Circuit Verification Engineer with a demonstrated history of working in the information technology and services industry. Skilled in UVM, System Verilog, Coverage driven verification, Microsoft Word, Perl Srcipting, C++, Automatic Test Pattern Generation (ATPG), and Assertion Based Verification. Strong engineering professional with a Master's degree focused in VLSI and Embedded System design from Gujarat technological university.
Stackforce AI infers this person is a VLSI and Embedded Systems expert with a focus on ASIC verification.
Location: Hyderabad, Telangana, India
Experience: 10 yrs 9 mos
Career Highlights
- Expert in UVM and System Verilog for ASIC verification.
- Strong background in VLSI and Embedded System design.
- Proven track record in coverage-driven verification methodologies.
Work Experience
SmartSoC Solutions Pvt Ltd
Principal Member of Technical Staff (2 yrs 9 mos)
Senior Design Verification Engineer (2 yrs 3 mos)
AMD
Senior Design Verification Engineer (1 yr 2 mos)
MosChip
ASIC Verification Engineer (1 yr 9 mos)
eInfochips (An Arrow Company)
ASIC Verification Engineer (9 mos)
Uurmi Group
Verification Engineer (2 yrs 1 mo)
Maven Silicon
Intern (3 mos)
Education
Master's degree at Gujarat technological university
Bachelor's degree (BE) at University of Mumbai
