Ajisha Sajeev — Software Engineer

Experienced Engineer with a demonstrated history of working in the semiconductor industry. Skilled in Object-Oriented Perl, Python, TCL, OCC, MBIST, LBIST, SSN, Test point insertion, System Verilog, Verilog, Joint Test Action Group (JTAG), synthesis, scan insertion, ATPG, FPGA, functional verification, Spyglass, formal verification and Universal Verification Methodology (UVM). Strong knowledge in the semiconductor industry with masters in micro electronics from BITS pilani (WILP) and post-graduate diploma from the national institute of electronics and information technology Calicut. -Experience in handling the DFT RTL insertion & validation. -Experience in handling block/chip level ATPG, Test coverage analysis, pattern verification with and without timing annotation. -Experience in generating the STUCK_AT, AT_SPEED, cell aware ,timing aware, N-detect and bridge pattern generation. -Experience in post silicon ATPG pattern bring up and debug. -Experience in EDT, OCC insertion techniques. -Experience in scan insertion. -Experience in SCAN STA constraints development. -Experienced in handling ATPG for USB, PCIE, HBM and DDR PHY IPs. -Experienced in handling DFT macro modelling.

Stackforce AI infers this person is a semiconductor design engineer with expertise in DFT and verification methodologies.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 7 mos