Chetan Chowdary Mandava

Software Engineer

Hyderabad, Telangana, India7 yrs 7 mos experience

Key Highlights

  • Expertise in SystemVerilog and UVM for design verification.
  • Patented innovations in IoT and AI-enabled products.
  • Proven track record in performance verification of complex systems.
Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on advanced design methodologies.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogPerformance Verification

Other Skills

AXIPythonLPDDR5Python (Programming Language)DDR5SVUVMMIPILinuxRTL-SDRAWS-IoTLFSRGTX TransceiverXilinx FPGAsInformation and Communications Technology (ICT)

About

I work as a Sr Design Verification Engineer with expertise in SystemVerilog, UVM and Python. I ensure to develop required expertise in team to deliver a quality RTL. I have an in-depth experience in AXI, AHB, LPDDR5, MIPI-CSI2 protocols. I am trying to build my expertise in PCIe, CLX, UCIe protocols. I hold two patents in IoT, AI enabled end user produi. I always ensure to improve skills and knowledge through a process of continuous learning.

Experience

7 yrs 7 mos
Total Experience
2 yrs 7 mos
Average Tenure
1 yr 3 mos
Current Experience

Nvidia

Senior Design Verification Engineer

Feb 2025Present · 1 yr 4 mos · Hyderabad, Telangana, India · On-site

Universal Verification Methodology (UVM)SystemVerilogAXIPython

Amd

Sr. Silicon Design Engineer

Jun 2023Feb 2025 · 1 yr 8 mos · Hyderabad, Telangana, India · Hybrid

  • I work on IP and SoC level verification of Processor Subsystem. I apply SV, UVM and Python to ensure the IP is verified to its every horizon.
  • I ensure the performance of the complete system is achieved. This helped me in gaining expertise on DDR5 protocol.
AXILPDDR5Universal Verification Methodology (UVM)Python (Programming Language)SystemVerilogDDR5

Amd india pvt ltd

Senior Design Engineer

Jun 2023Feb 2025 · 1 yr 8 mos

  • Executed complete performance verification for ISP at both block and SoC levels, ensuring bandwidth targets for LPDDR5 and MIPI interfaces. Developed a PMU counter analysis framework for CMN (Coherent Mesh Network) to validate diverse BW scenarios and bottleneck identification. Orchestrated the complete Testbench (TB) bring-up for derived projects, integrating the VIPs, BFMs, performance monitors and automated checkers. Architected Python-based automation suites for coverage closure, reducing the time-to-market by accelerating the functional coverage from 90 to 100 percent. Acted as a technical mentor and lead, providing comprehensive training to new joiners and scaling team capabilities in SV, UVM, AXI.

Qualcomm

2 roles

Design Verification Engineer

Dec 2020Jun 2023 · 2 yrs 6 mos

AXIUniversal Verification Methodology (UVM)Python (Programming Language)LinuxSystemVerilog

Associate Engineer

Nov 2018Dec 2020 · 2 yrs 1 mo

Indian institute of technology, hyderabad

Summer Research Fellow

May 2017Jul 2017 · 2 mos · Hyderabad Area, India

  • Implementation of Opportunistic MAC protocol for M2M communication in WiFi white spaces.

Indian institute of science (iisc)

Winter Intern

Dec 2016Jan 2017 · 1 mo · Bangalore, India

  • Radio Astronomy using RTL-SDR Raspberry pi and Amazon AWS-IoT.
Linux

Defence electronics research laboratory

Summer Intern

May 2016Jul 2016 · 2 mos · Hyderabad Area, India

  • Learn the Implementation of LFSR (Linear Feedback Shift Register), Monobit Sampling Using GTX Transceiver on Xilinx Virtex-4, 5, 7 FPGAs. The total work is carried on Vivado and Xilinx ISE software's.
Universal Verification Methodology (UVM)LinuxSystemVerilog

Education

National Institute of Technology Hamirpur-Alumni

Bachelor of Technology (BTech) — Electronics And Communication Engineering

Jan 2014Jan 2018

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