Meghana TJ

Software Engineer

Bengaluru, Karnataka, India2 yrs 2 mos experience

Highly Stable

Key Highlights

Expert in ASIC design verification methodologies.
Proficient in SystemVerilog and UVM for functional verification.
Experience with multiple high-impact projects in telecommunications.

Stackforce AI infers this person is a skilled ASIC Verification Engineer with expertise in telecommunications and automotive industries.

Contact

Skills

Core Skills

AsicFunctional Verification

Other Skills

ASIC VerificationSystemVerilogUVMSynopsys VCSQuestaSimMultiport Gigabit Ethernet SwitchMultiport Ethernet SwitchCAN/CANFD ControllerVerification Environment DevelopmentSynopsys MAC VIPTest Plan DevelopmentCoverage AnalysisVerilogUniversal Verification Methodology (UVM)Very-Large-Scale Integration (VLSI)

About

Currently pursuing masters in Electrical and Computer Engineering. Experienced in ASIC/IP/Subsytem design verification. Familiar with protocols like Gigabit Ethernet, Ethernet, AXI, PCIe, APB, CAN, CANFD Knowledge in the implementation of constrained random verification methodologies and functional coverage driven verification environments using SystemVerilog, UVM . Worked with the tools: Synopsys VCS , Synopsys Verdi , Questa Sim , Xilinx Vivado, Cadence Virtuoso

Experience

2 yrs 2 mos

Total Experience

2 yrs 2 mos

Average Tenure

Current Experience

Nvidia

ASIC Verification Engineer

Jul 2021 – Sep 2021 · 2 mos · Massachusetts, United States

ASIC VerificationSystemVerilogUVMSynopsys VCSQuestaSimASIC+1

University of southern california

Student Worker

Jan 2021 – May 2021 · 4 mos · California, United States

Tata elxsi

Design Verification Engineer

Oct 2017 – Dec 2019 · 2 yrs 2 mos · Bangalore

> Was part of 3 projects : Multiport Gigabit Ethernet Switch, Multiport Ethernet Switch , CAN/CANFD Controller
> Worked on the verification env development of multiport Ethernet Switch, included features like Flow Control, Time stamping, TAS, CBS, Pre-emption, Error Handling, Station Management, Link Verification, Low Power Idle, VLAN Tag/Untag etc.
> Integrated Synopsys MAC VIP to the verification Environment.
> Developed the verification architecture documents for Ethernet and PHY IPs
> Developed the Stimulus plan, Test plan, Coverage plan, Assertion plan for Ethernet and PHY IPs.
> Implemented the ISR environment for the complete subsystem.
> Coded verification environment components like Stimulus, RX and TX handlers, error monitor and handling of the ethernet errors, scoreboard, coverage, etc.
> Coded the RAL and Register Read Write testcases for Ethernet and PHY IPs
> Wrote the sanity, basic , medium and advanced testcases for Ethernet/PHY
> Presented the architecture documents and plans to the clients
> Communicated with the clients to clarify the doubts in the specifications and the bugs found
> Analyzed coverage holes to achieve 100% coverage
> Mentored the newcomers of the team
> Guided the peer members of the team to resolve the dependencies
> Reviewed the code files and plans of the peers in the team.
> Extended debugging help for the peers in the team.
> Worked on the coverage module of the CAN Controller

Multiport Gigabit Ethernet SwitchMultiport Ethernet SwitchCAN/CANFD ControllerVerification Environment DevelopmentSynopsys MAC VIPTest Plan Development+3