Naveen Venneti

Director of Engineering

Bengaluru, Karnataka, India18 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Director of R&D with extensive ASIC expertise.
Proficient in VLSI and Physical Design methodologies.
Strong background in RTL design and verification.

Stackforce AI infers this person is a VLSI and ASIC design expert with leadership experience in semiconductor engineering.

Contact

Skills

Core Skills

AsicVlsi

Other Skills

VerilogPhysical DesignStatic Timing AnalysisPhysical VerificationIntegrated Circuit DesignTimingLogic DesignLVSSoCSystemVerilogFPGAEmbedded SystemsSimulationsTiming ClosureTCL

Experience

18 yrs 1 mo

Total Experience

2 yrs 3 mos

Average Tenure

4 yrs 2 mos

Current Experience

Synopsys inc

3 roles

Director R&D Engineering

Promoted

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India

ASICVerilogPhysical DesignStatic Timing AnalysisVLSIPhysical Verification+26

Sr. Manager, R&D

Promoted

Feb 2023 – Feb 2025 · 2 yrs · Bengaluru, Karnataka, India

R&D Engineer Sr. Staff

Apr 2022 – Feb 2023 · 10 mos · Bengaluru, Karnataka, India

Cadence design systems

2 roles

Sr Principal Application Engineer

Promoted

Jul 2021 – Apr 2022 · 9 mos

Principal Application Engineer

Sep 2017 – Jul 2021 · 3 yrs 10 mos

Intel corporation

Technical Analyst

Apr 2015 – Sep 2017 · 2 yrs 5 mos · Penang, Malaysia

Qualcomm

Physical Design Engineer

May 2014 – Apr 2015 · 11 mos · Bengaluru, Karnataka, India

Amd

Physical Design Engineer

Nov 2011 – Apr 2014 · 2 yrs 5 mos · Greater Hyderabad Area

Mindtree ltd.

Senior Physical Design Engineer

Feb 2011 – Dec 2011 · 10 mos

Infotech

Physical Design Engineer

Jul 2008 – Feb 2011 · 2 yrs 7 mos

Bombardier transportation

Intern

May 2007 – Aug 2007 · 3 mos

Education

Syracuse University

M.S. — Computer Engineering

Jan 2006 – Jan 2008

Jawaharlal Nehru Technological University

B.Tech — Electronic and Communications Engineering

Jan 2002 – Jan 2006

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