Nagendra Chandrakar — Design Manager

-High speed clocking circuits and methodology development -Worked in Qualcomm DSP processor design group; Leading the physical design activity of modem coprocessor. -Involved in 20+ Tapout in different technologies (65 nm to 14nm) of various design including AMD’s high speed processor, Qualcomm MSM/MDM soc -Successfully Implementation and Tapeout of “ a brand new architecture of software defined modem processor” - Experience in both ASIC and high-speed Microprocessors designs (Qualcomm DSP and AMD x86 processor ) - Worked in the P&R and STA for both block and SOC level design - Expertise in custom clocking for high speed microprocessor and regular CTS - Experience in latch based design - Low power design methodology development - High Seed custom Memory , FIFO and Clock tree macro design (32 nm & 40nm in AMD) - Source synchronous bus implementation - IR and power analysis - Design/functional eco and timing eco flow

Stackforce AI infers this person is a VLSI design expert specializing in ASIC and SoC development.

Location: Bengaluru, Karnataka, India

Experience: 19 yrs 10 mos