Hemendra Kumar

Product Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in ASIC design and physical verification.
Proficient in multiple Cadence tools for VLSI.
Strong background in research and practical applications.

Stackforce AI infers this person is a Semiconductor and Aerospace professional with expertise in ASIC design and physical verification.

Contact

Skills

Core Skills

Asic DesignPhysical DesignSynthesisLecIc Fabrication

Other Skills

icc2fusion compilerECOPhysical VerificationDC SynthesisLogical Equivalence CheckingSimbuildDesign CompilerConformalRTL to GDSII conversionCadence toolsInnovusTempusIncisiveGenus

About

Experienced in Synthesis, Logical equivalence checker (LEC), Physical design and ECO as contingent worker at Intel. Experienced Research Associate with a demonstrated history of working in the higher education industry. Skilled in verilog, VHDL, C, Application-Specific Integrated Circuits (ASIC), and Cadence tools, Innovus, Genus, nclaunch, Confirmal, Encounter Test, SimVision, Cadence Virtuoso tool. Strong research professional with a M.tech focused in VLSI and Embedded System from svnit surat.

Experience

9 yrs 10 mos

Total Experience

2 yrs 2 mos

Average Tenure

9 mos

Current Experience

Sintegra inc.

ASIC Design Engineer

Sep 2025 – Present · 9 mos · Bengaluru, Karnataka, India · Hybrid

Working for the Meta client as contingent worker

Cyient

Senior Physical Design Engineer

Dec 2024 – May 2025 · 5 mos · Bengaluru, Karnataka, India

Capgemini

ASIC Physical Design Engineer

Jul 2021 – Dec 2024 · 3 yrs 5 mos · India

icc2fusion compilerASIC DesignPhysical Design

Intel corporation

2 roles

Contingent worker

May 2019 – Jan 2020 · 8 mos · Bangalore

I have some practical work to fix ECO and it helps to fix setup and hold violation. I switched to another project to do physical verification work to fix DRC and LVS violations.

Contingent Worker

Jun 2018 – Dec 2018 · 6 mos · India

DC Synthesis and LEC have done for different sub-systems for 14 nm and 7 nm technologies. Tools used: Simbuild, Design Compiler of Synopsys and Conformal tools of cadence.

Altran

Physical Design Engineer

May 2018 – May 2022 · 4 yrs · Bangalore India

Svnit surat

Research Associate

Apr 2016 – May 2018 · 2 yrs 1 mo · SVNIT SURAT

Worked on the ISRO project to fabricate IC in Semi-Conductor Laboratory (SCL). This project required to convert RTL files to GDSII files by using different cadence tools such as Innovus Implementation System for Physical Design, Tempus for Static timing analysis and other used tools are Incisive, Genus Synthesis Solution, Encounter Test, Confirmal Logical Equivalence Checker.