Anjali Arora

Technical Program Manager

Bengaluru, Karnataka, India20 yrs 10 mos experience
Highly Stable

Key Highlights

  • Over 20 years in semiconductor IP design and program management.
  • Expert in driving cross-functional technical programs.
  • Strong hands-on experience in analog and mixed-signal circuit design.
Stackforce AI infers this person is a seasoned Semiconductor Program Manager with deep expertise in EDA methodologies and cross-functional leadership.

Contact

Skills

Core Skills

Program ManagementRisk ManagementCustomer Relationship ManagementIntegrated Circuit Design

Other Skills

CommunicationStrategy ExecutionModemCustomer Relationship Management (CRM)TFMEngineeringProject PlansLDOMemoryLeadershipManagementMixed-Signal Integrated CircuitsSystemVerilogMixed SignalASIC

About

With more than 20 years of experience across semiconductor IP design, program management, and EDA/CAD methodology, I’ve built a career focused on learning, problem-solving, and creating solutions that unite technology and leadership. At Qualcomm, I serve as a Staff Program Manager, to drive strategic execution of complex, cross-functional technical programs: from concept to release. My focus includes program planning, resource and budget management, risk mitigation, and cross-team collaboration and execution towards common goal. I specialise in simplifying complexity, driving teams alignment across geography and translating insights into clear, actionable outcomes for senior leadership. Previously, at Intel, I led CAD Engineering for Analog/Mixed Signal/RF IPs, managing a high-performing team responsible for end-to-end CAD enablement, supporting IP design across different market segments(server/compute/graphics) and methodology development. From PDK integration to validated CAD flow releases, promoted execution through Agile frameworks (Jira, Scrum, CI/CD) while fostering collaboration across design, CAD, and methodology teams globally. Earlier in my career, as a Design Engineer, I gained hands-on experience in analog and mixed-signal circuit design (Amplifiers, LDO Regulators) and developed deep expertise in EDA tools and flow architectures, experience that continues to ground my technical judgment and strategic decision-making. Passionate Technical Program Manager with strong hands-on technical expertise. - Experienced in analog/mixed-signal design, spice simulation, mixed signal, layout verification, debugging, and automation. - Demonstrated excellence in Customer Relationship and Success Management, fostering long-term partnerships and measurable customer outcomes. - Skilled in Verilog/VHDL, scripting, and macro-modeling. - Proficient with Cadence Virtuoso, Spectre, AMS Designer, ADS, and GoldenGate and more - Background across design, application engineering m, validation, and R&D roles. - Deep understanding of the semiconductor design and validation process. As a leader, I believe in empowering teams through clarity, trust, and ownership. I enjoy mentoring engineers, fostering innovation, and ensuring that process excellence translates into tangible business impact.

Experience

20 yrs 10 mos
Total Experience
3 yrs 7 mos
Average Tenure
3 yrs 7 mos
Current Experience

Qualcomm

Staff Program Manager

Nov 2022Present · 3 yrs 7 mos · Bengaluru, Karnataka, India

Program ManagementRisk ManagementCommunicationStrategy ExecutionModem

Intel corporation

CAD Engineering Manager

Nov 2019Nov 2022 · 3 yrs · Bangalore

Customer Relationship Management (CRM)Program ManagementTFMEngineeringCommunicationCustomer Relationship Management

Keysight technologies

R&D Engineer

Sep 2013Nov 2019 · 6 yrs 2 mos · Manesar, Gurgaon

  • RnD engineer
  • Scrum master for agile team
  • Worked as QA engineer for Analog and RF flows
  • for automated and manual testing
  • Flow demos to customer on Analog and RF flows using GoldenGate and ADS.
  • Testing and Qualifying Product releases.
  • Testing using automated and manual methods
  • Maintaining and running regression test suites (FURPS)
  • Debugging customer issues, driving through the release cycles through scrums
Engineering

Cadence design systems

2 roles

Senior member of Technical Staff

Dec 2012Sep 2013 · 9 mos

  • Worked as 'Product Validation' engineer for Cadence QRC extraction.
  • Responsible for testing existing new features for QRC.
  • Running and maintaing existing functional and accuracy regressions.
  • Creating regressions for new features.
Project Plans

Lead Application Engineer

Sep 2007Nov 2012 · 5 yrs 2 mos

  • Worked in Custom IC Analog Mixed Signal Group
  • Customer issues handling for Spectre, APS, Spectre RF, Ultrasim, AMS Designer (including HDLs Verilog/VerilogA/Verilogams/VHDL and Systemverilog etc), Relxpert.
  • Customer issues handling Virtuoso ADE-L(OA and CDBA), ADE-XL/GXL
  • Working with R&D on internal/customer reported issues
  • Worked as Expert to expert (E2E) with Tier1 customers.
  • Training delivery to customers on Cadence products.

Arm

Consultant

Jan 2006Jan 2007 · 1 yr

  • Memory Characterization

Tata elxsi ltd.

Senior Engineer

Jul 2005Sep 2007 · 2 yrs 2 mos · Bangalore

  • Worked as Senior Engineer in Analog Mixed Signal Group.
  • Worked on Power Management Circuit Design ( LDO, Boost Converter, Amplifiers, Bandgap Reference)
  • Worked on Macro-modelling for power management circuits
  • Standard Cell Characterization
Integrated Circuit DesignLDOMemory

Education

Thapar Institute of Engineering & Technology

Master's degree — VLSI DESIGN AND CAD

Apr 2003Apr 2005

Thapar Institute Of Engg and Technology

M.Tech — VLSI and CAD

Jan 2003Jan 2005

Kurukshetra University

B.Tech — Instrumentation and Control

Jan 1998Jan 2002

Thapar Institute of Engineering & Technology

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