G Rajath Kumar

CEO

Bengaluru, Karnataka, India0 mo experience

Key Highlights

Strong foundation in VLSI and ASIC design.
Proficient in Verilog and Static Timing Analysis.
Education from JSS Academy of Technical Education.

Stackforce AI infers this person is a VLSI design engineer with a focus on ASIC development.

Contact

Skills

Other Skills

Application-Specific Integrated Circuits (ASIC)TimingStatic Timing AnalysisVery-Large-Scale Integration (VLSI)HardwareVerilogIntegrated Circuits (IC)

Education

JSS Academy Of Technical Education Karnataka

Aug 2019 – Aug 2023

JSS Academy Of Technical Education Karnataka

Bachelor of Engineering - BE — Electronics and communication

Jan 2019 – Present

Stackforce found 100+ more professionals with Application-Specific Integrated Circuits (ASIC) & Timing

Explore similar profiles based on matching skills and experience

Chethan R

Project Engineer

at Wipro

Bengaluru, India1 yr 11 mos exp

Universal Verification Methodology (UVM)RTL Design

Sanket Tekawade

Digital Design Engineer

at Google

Bengaluru, India2 yrs 10 mos exp

Tanaya Mehta

Physical Design Intern

at Siemens EDA (Siemens Digital Industries Software)

Bengaluru, India2 yrs 6 mos exp

Physical DesignASIC

Akshay Kaushik

Silicon Design Engineer - 2

at AMD

Bengaluru, India3 yrs 8 mos exp

Functional VerificationSystem on a Chip (SoC)Cloud ServicesMobile Application DevelopmentTesting and Validation

Daivik Reddy Bhaskar

Physical Design Intern

at ChipEdge Technologies Pvt Ltd

United States0 mo exp

RTL-to-GDSIIStatic Timing AnalysisPhysical Design

Deepa Mariam Thomas

Solutions Engineering Staff Design

at Arm

India14 yrs 7 mos exp

VLSIRTL design

Hari Krishna Vinjamoori

Asic implementation Engineer

at Sintegra Inc.

Bengaluru, India6 yrs 7 mos exp

ASICPhysical DesignPhysical VerificationVLSI

Taha Perwaiz

Physical Design Engineer

at Qualcomm

Bengaluru, India2 yrs 3 mos exp

Physical DesignTiming ClosureGraphics Hardware DesignDigital IC DesignPower Performance Optimization