Dayananda YS

Founder

India18 yrs 2 mos experience
Highly Stable

Key Highlights

  • Founder of ASIC end-to-end solutions company
  • Expert in SoC verification and RTL design
  • Extensive experience in low-power design methodologies
Stackforce AI infers this person is a Semiconductor expert with a focus on ASIC and SoC design and verification.

Contact

LinkedIn

Skills

Core Skills

AsicSoc

Other Skills

Field-Programmable Gate Arrays (FPGA)System on a Chip (SoC)SystemVerilogVHDLLow-power DesignRTL DesignSynthesisSoC IntegrationLow power designsUPF creationLinuxCSV-UVMIntegrationDebugging

About

RTL Design, SoC Integration, Synthesis, SDC, Spyglass, GLS, CDC, LEC, Formality, FPGA, Post Silicon-ATE IP Verification, SoC Verification, C, SV, UVM UMA, OMAP, Dolphin, JPEG, JPEG-XR Socs, Sumeru, Lynx, Pegasus, Meteor, Shapiro, Talisker, IBIS, Smarti9, Scorpio, Orion

Experience

18 yrs 2 mos
Total Experience
2 yrs 7 mos
Average Tenure
--
Current Experience

Pppasschip technologies private limited

Founder and CEO

Oct 2020 – Aug 2024 · 3 yrs 10 mos · Bengaluru

  • Offering services in : ASIC End to End Solutions :
  • RTL Design - Coding in Verilog, System Verilog, Low power designs, UPF creation, Synthesis, SoC Integration, SDC, Spyglass Lint, CDC, RDC, GLS, LEC, Formality, FPGA implementation, Post Silicon-ATE
  • IP Verification, SoC Verification, C, SV, UVM based Environments, Formal Verification, Low power verification
  • Methodology, Automation, EDA flow setup
ASICField-Programmable Gate Arrays (FPGA)System on a Chip (SoC)SystemVerilogVHDLLow-power Design+1

Broadcom inc.

SoC Verification Engineer at Broadcom Inc.

Oct 2018 – Oct 2020 · 2 yrs · Bengaluru Area, India

  • C, SV-UVM based on SoC Verification.
  • ATE Pattern generation, Silicon Debug
LinuxSoC

Intel corporation

Consultant Team Manager

Mar 2017 – Oct 2018 · 1 yr 7 mos · Bengaluru Area, India

  • IBIS SoC Verification, IBIS GLS, Smarti9 SoC Verificaion SV, UVM

Knowles intelligent audio

Staff Engineer

Feb 2016 – Feb 2017 · 1 yr · Bengaluru Area, India

  • Micro Architecture, RTL Coding

Broadcom inc.

Consultant Engineer

Jul 2013 – Feb 2016 · 2 yrs 7 mos · Bengaluru Area, India

  • Worked on RTL Design for Data Cache of Cortex M0
  • ARM Network Interconnect generation using Adcanvas and and support
  • Front end activities : Spyglass, Integration, Synthesis, LEC & GLS
  • Synthesis of subsystem
  • Constraints ( SDC ) and support for timing closure
  • Business Development

Sandisk

Staff Verification Engineer

Oct 2010 – May 2013 · 2 yrs 7 mos · Bengaluru Area, India

  • Lead RnD Team for Enhancing Nand Endurance
  • Lead and Developed VIP for AHB Master-Slave-Monitor using SV-VMM

Samsung india software operations ltd

Technical Lead

Sep 2006 – Oct 2010 · 4 yrs 1 mo

  • Worked on S3CR650A,S3CR650B for Soc integration, system level verification.
  • Verification of S3C2680X Soc.

Texas instruments

2 roles

Senior Design Engineer

Mar 2005 – Sep 2006 · 1 yr 6 mos

  • Worked on UMA2.2, UMA3.0, OMAP2420, OMAP 3430 SoCs. Involved in Design, Synthesis, Netlist Simulations, Formality, and similar activities.

Design Engineer

Mar 2004 – Mar 2005 · 1 yr

  • Worked on Few IPs of UMA2.2, 3.0 and on some IPs of OMAP2420.

Education

National Institute of Technology Karnataka

M.Tech — Industrial Electronics [ Dept of ECE ]

Jan 2000 – Jan 2002

Bangalore University

SIT - Siddaganga Institute of Technology

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