Santhosh Muthaian — Director of Engineering
Experienced Analog/Mixed signal IC Layout design in 16nm FinFet technology. Experienced Analog/Mixed signal IC Layout design in 28nm Mosfet technology. Experienced Analog/Mixed signal IC Layout design in 65nm technology node. Have developed layout of Differential Amplifiers, Current Mirrors, Biasgen blocks etc. Familiar with scripting language, Cadence SKILL and Pyxis Ample. Good working knowledge of Linux OS, shell scripts and Python programming. I have been exposed to industry standard EDA tools like Cadence Virtuoso Layout XL, Pyxis Layout, Calibre, Cadence Allegro, gEDA PCB. Independent and ability to take on responsibility.
Stackforce AI infers this person is a skilled Analog IC Layout Engineer with expertise in advanced semiconductor technologies.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 1 mo
Career Highlights
- Expert in Analog/Mixed Signal IC Layout Design
- Proficient in multiple technology nodes including 16nm FinFET
- Experienced with industry-standard EDA tools
Work Experience
Marvell Technology
Senior Manager (1 mo)
Staff Engineer (2 yrs 1 mo)
Qualcomm
Senior Layout Engineer (1 yr 7 mos)
Texas Instruments
Analog Layout Engineer (4 yrs 4 mos)
Altran
Analog RF layout design (1 yr)
Signalchip Innovations
Analog Layout Design Engineer (1 yr)
Education
Master of Technology - MTech at BITS Pilani Work Integrated Learning Programmes
Bachelor's degree at RNSIT, Bangalore