Uby H

Product Engineer

Bengaluru, Karnataka, India1 yr 5 mos experience
Most Likely To Switch

Key Highlights

  • Expert in Digital Circuit Design and VLSI.
  • Proficient in SystemVerilog and design verification.
  • Strong programming skills in C, Java, and Python.
Stackforce AI infers this person is a VLSI and Embedded Systems engineer with strong design verification expertise.

Contact

Skills

Core Skills

Design VerificationSystemverilogEmbedded Systems

Other Skills

Joint Test Action Group (JTAG)XcelliumVerilogAnalog Circuit DesignJaspergoldSimvisionVerification IPVery-Large-Scale Integration (VLSI)Computer ArchitectureDigital Circuit DesignAssembly LanguageC (Programming Language)Static Timing AnalysisCDCOpenROAD

About

I am really well versed with digital circuit design. I have a strong hold on Analysis and design of Digital Circuits (ADDC), Verilog (HDL), Digital VLSI Design (DVD) and Low power VLSI design and architecture . I am well aware of RTL to GDS flow in VLSI Design and the tools used such as Cadence Virtuoso, Bambu, Yosys, Xilinx Vivado, GTK wave, Icarus, OpenSTA, LTSpice, Logism, OpenROAD, and many more. I am also aware of design verification, and well versed with System Verilog, System Verilog assertions and UVM. I am currently exploring UPF. I am passionate about Computer Architecture and Organization. Have explored multiple concepts of processor design, ISA, Memory architecture, Memory hierarchy and so on. Worked on a project of RISCV pipelined CPU core with forwarding unit and modeled the same using Verilog. Apart from this I am also aware of bus architectures. I have explored AMBA bus protocols (AHB, APB, ASB, AXI ,etc), I have also implemented a basic APB bus protocol using Verilog. Continuously learning and moving ahead in this domain, currently learning about OOO instruction execution, multicore CPU, vector processing and GPU architecture and programming. I have a strong hold on coding and programming languages. I have mastered many languages which include - C, JAVA and Python. I am an active DSA learner and I have done data structures and algorithms in C and JAVA. I am well versed with different IDE's such as Xcode, Visual Studio Code, BlueJ, etc. Along with this I am also familiar with HTML and CSS, I have designed a portfolio website using HTML and CSS. I am good at Embedded Systems and Computer Architecture having completed several courses in the same . I am also equipped with PCB designing using Altium software. I have designed multiple PCB's and am actively involved in projects of Embedded System design. I am good at Embedded C and Assembly language. My GitHub profile link - https://github.com/ubyhzargam My Leetcode profile link - https://leetcode.com/ubyhzargam/ My GeeksforGeeks profile - https://auth.geeksforgeeks.org/user/ubyhza2adz My figma profile link - https://figma.com/@ubyzargam My Quora profile link - https://www.quora.com/profile/Uby-H

Experience

1 yr 5 mos
Total Experience
8 mos
Average Tenure
11 mos
Current Experience

Skyworks solutions, inc.

2 roles

Design Verification Engineer 1

Jul 2025Present · 11 mos

  • 1. Verified the JTAG controller by integrating JTAG VIP into a scratch-built SystemVerilog testbench; configured the VIP using the SOMA file created using Pureview tool.
  • Developed testcases to verify the JTAG TAP controller in full-chip integrated DUT and wrote testbenches for other blocks.
  • Enabled gate-level simulation (GLS) support in the testbenches, executed GLS runs, and debugged results.
  • Finally, analysed coverage using imc, vmgr and identified coverage holes.
  • 2. Bring up of forward connectivity test using Cadence Jaspergold connectivity tool. Visualised and analysed all the connections using the tool. Debugged the failures and reported the bugs.
  • 3. Performed sequential equivalence checking (SEC) for a block using Cadence JasperGold SEC app for verifying spec and implementation with clock gating and analysed the results.
  • 4. Verified clock gating of a block by writing system verilog assertions. Debugged and analysed fullchip testcases with the written assertions. Created cover bins and cover properties to analyse coverage.
Joint Test Action Group (JTAG)XcelliumDesign VerificationSystemVerilog

Design Verification intern

Jan 2025Jul 2025 · 6 mos

  • 1. Executed comprehensive register-level verification including power-on-reset (POR) default value validation, read/write accessibility testing, and systematic debugging of functional anomalies. Leveraged Perl and Python scripting for automation, SystemVerilog for testbench development, and utilized Cadence Xcelium simulator with SimVision waveform analyzer.
  • 2. Reviewed, debugged, and enhanced existing testbenches to verify functionality and use cases of SPI and UART controllers within the IC design.
  • 3. Automated UVM testbench skeleton generation using Python with Jinja2 templating, JSON parsing, Verible parser, and libraries including tkinter, sys, os, re for scalable verification infrastructure.
  • 4. Developed testbench architecture framework for comprehensive UART controller verification and validation.
  • 5. Implemented waivers for livelock and deadlock properties in Cadence JasperGold using Tcl scripting and analyzed temporal properties in RTL design files.
  • 6. Developed Python script for automated error extraction from regression log files and generated structured CSV reports for debugging analysis.
  • 7. Automated the generation of UML diagrams to model design and testbench architecture using custom Python scripts.
XcelliumVerilogDesign VerificationSystemVerilog

Wildsonic

Field application engineer intern

May 2024Aug 2024 · 3 mos · Bengaluru, Karnataka, India · Hybrid

  • Work focuses on verification and testing of embedded products - Hardware and Firmware. Tools used - Daplink board, Tera term, VS Code, C, C++, WSL, GitBash, Audacity, Digital multimeter, Power profiler kit, Solar panels, ublox LARA-R280, m-center (AT commands) , 18650 and 21700 Li ion batteries etc
Embedded SystemsAnalog Circuit Design

Entrepreneurship cell, rvce

Junior Associate

Jun 2022Dec 2022 · 6 mos · Bengaluru, Karnataka, India

  • Was a member of Ecell at RVCE. Vertical - Marketing and PR.

Scenes (previously avalon meta)

Customer onboarding specialist

Mar 2022Apr 2022 · 1 mo · Bengaluru, Karnataka, India

  • I helped some of the top companies in the world grow their communities.

Education

RV College Of Engineering

Bachelor of Engineering - BE

Nov 2021Jul 2025

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