Hemamali Gorthi

Director of Engineering

Bengaluru, Karnataka, India20 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 17+ years in wireless systems design and SoC productization.
  • Expertise in MIMO WLAN and low power IoT systems.
  • Proven leadership in cross-functional team management.
Stackforce AI infers this person is a seasoned expert in wireless telecommunications and IoT systems design.

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Skills

Core Skills

Indoor Location TrackingIotWlan Mimo SocsSystems Design EngineeringWlan Mimo Phy/radio SystemsWlan Systems DesignTelecommunicationsWireless Systems Design

Other Skills

SiliconAlgorithmsHardwareEmbedded SoftwareCloudPAPD calibration algorithmsPHY/MAC AlgorithmsBoard DesignFirmware DesignMIMO Receive algorithmsSimulation/characterization test benchDesign and silicon performance characterizationAGC/Carrier sense/Freq-Est algorithmsLDPC/Viterbi decoding algorithmsCarrier detection algorithms

About

17+ years of industrial research, wireless systems design, SoC productization, customer interface and management experience in 802.11x SISO/MIMO WLAN, 802.15.4a IR-UWB based systems. Extensive experience in OFDM PHY(L1) transceiver, RF calibration and Cross-Phy coexistence/interference resilience algorithms, SoC performance enhancements and power/area optimizations for embedded/router products, Hardware/Board design validation, embedded firmware design/debugging Good experience in defining and development of low power indoor positioning IoT systems, development of proprietary wireless MAC/Network(L2/L3) protocols and EDGE device computing software. Tech.Specialties: o Communication and Signal Processing Algorithms for MIMO WLAN Systems  PHY Transceiver: AGC, Carrier sense, Frequency estimation, timing synchronization, Channel Equalization, ZF/ML Decoder, TDoA algorithms, Location Engine, RF Control/Sequencing, PHY packet FSM design etc  Radio Calibrations: RSSI,ACI,IQ/LOFT/PAPD/Tx power control/ET calibrations  SoC: Silicon/Board bring-up and full system performance characterization and power optimization across PVT corners, effective WLAN/BT/FM/ Cellular coexistence schemes/algorithms, RTL/FPGA development, real time deep exposure to L2/L3 protocols and PMU PS modes, on site customer platform debugging/support  Exposure to various types of WiFi product lines, Ex Embedded(HSIC,SPI,SDIO), Retail(USB, PCIe), Enterprise(AP) o IOs: worked closely with SDIO 2.0, SPI, UART, I2C, JTAG etc and high speed interfaces USB, PCIe, SDIO3.0, Quad-SPI etc. o Tools: MATLAB, C, C++, Python, QT/FPGA, RTL design debugging tools like SimVision etc, OTA tput analysis tools WireShark, Airopeek, Chariot etc. o Embedded IoT Platforms: Particle Photon-STM32 ARM Cortex M3, Raspberry Pi 3, ST-MEMs o Additional Skills: Team oriented and self dependent working style, excellent mentoring, team building and leadership skills.

Experience

20 yrs 7 mos
Total Experience
4 yrs 1 mo
Average Tenure
4 yrs 3 mos
Current Experience

Infineon technologies

Director

Mar 2022Present · 4 yrs 3 mos · Bengaluru, Karnataka, India

Nxp semiconductors

Director

Oct 2019Mar 2022 · 2 yrs 5 mos · Bangalore

Trakray innovations pvt.ltd

CTO and Founder

May 2015Sep 2019 · 4 yrs 4 mos · Bengaluru Area, India

  • # TrakRay is an Indoor Location Tracking technology and IoT company covering Silicon, Algorithms, Hardware, Embedded Software and Cloud targeting the requirements of industrial IoT market space
  • like asset/human tracking in warehouses/smart factory/hospitals, keyless automobile entry etc
  • # Conceptualized and developed precise 3D Indoor Location Tracking systems based on IEEE 802.15.4a/802.15.6 IR-UWB and WiFi technologies
  • ## System side efforts includes fine timing/CSI algorithm changes, post silicon validation and wide band radio characterisation, design of hyperbolic multilateration and novel wireless synchronisation algorithms(patent filing pending), TDoA based hybrid location estimation engine, kalman filtering etc..
  • ## Responsible for coming up with specifications for TAG, Anchor and Edge processor hardware platforms and driving associated embedded/cloud software changes
  • ## Worked on Dynamic Anchor Geometry Selection for best TAG location estimation accuracy in a TDoA based RTLS deployment – Patent filing pending
  • # Worked on providing high position accuracy (10-30cm), low power and low cost, hybrid wireless localisation systems based on UWB + WiFi SoCs
Indoor Location TrackingIoTSiliconAlgorithmsHardwareEmbedded Software+1

Broadcom india pvt.ltd

3 roles

Sr.Principal/Manager Systems Design Engineering

Jul 2011May 2014 · 2 yrs 10 mos · Bengaluru, India

  • Sr.Principal, Systems Design Engineer:-
  • # Responsible for development and productizing of PAPD calibration algorithms (Power
  • Amplifier linearization) for first generation 40nm internal PA WLAN MIMO SoCs
  • # Provided scalable algorithms/solutions to real world challenges like ACI, BT-Coex, Cellular/FM
  • Blocker performance improvements and PS modes
  • # Involved in the design changes of PHY/MAC Hardware assisted virtual simultaneous dual
  • band (VSDB) to enable new applications like Miracast/WFD
  • # One of key system architect in defining wave-1 802.11ac MIMO RSDB and 160Mhz mode
  • operations for WLAN embedded SoC
  • # Studied the algorithm changes to advanced PA linearization techniques such as Wide Band
  • digital PAPD + Envelope Tracking(ET) blocks to improve the Power Amplifier(PA) efficiency on a
  • 40nm 11ac iPA SoC
  • Manager, Systems Design Engineering:-
  • # Responsible for development and deployment of 1st generation low power 40nm 802.11n
  • MIMO dual band WLAN (iPA) + BT integrated combo SoC systems, targeted for tablet market
  • space.
  • # Lead systems team size of 8 and driven global cross functional team of 20+
  • engineers (i.e VLSI/MAC/FW/ Radio/Board Hw Automation/FAE) to achieve best possible
  • WLAN SoC system performance.
  • ## Primary responsibilities includes PHY/MAC Algorithms, Board, Firmware Design and
  • verification and SoC bring up/customization
  • # First time in industry to productize MIMO SoC with relatively premature SDIO 3.0 host
  • interface
  • # One of the key person for generating ~400M$ revenue through low power 2x2 MIMO
  • embedded products and worked closely with top mobile/embedded customers
PAPD calibration algorithmsWLAN MIMO SoCsPHY/MAC AlgorithmsBoard DesignFirmware DesignSystems Design Engineering

Sr Staff - Systems Design Engineer

Promoted

Mar 2009Jul 2011 · 2 yrs 4 mos · Bengaluru, India

  • # Responsible for architecting and productization of adaptive and scalable low power MIMO Receive
  • (AGC/CRS/DEMOD/RFSeq/RFCtrl/FSM) algorithms – Breaking the "battery power limitation barrier"
  • for MIMO SoCs in order to enter into embedded product space
  • ## * Multiple patents are filed on this area of work
  • # Worked on optimizing ML decoder algorithms (without performance loss) to meet low power and
  • cost requirements of a 2x2 MIMO SoC that targeted for embedded applications
  • # Owned WLAN MIMO PHY/RADIO systems performance simulation/characterization test bench (fixed
  • point C/matlab)
  • ## Helped VLSI team in cross verification of their verilog design models against fixed point
  • C/C++ models and responsible for bit accuracy of complete PHY transceiver data/control path
  • # Part of various onsite customer debug camps to resolve PHY/MAC/Firmware/Board level issues
MIMO Receive algorithmsWLAN MIMO PHY/RADIO systemsSimulation/characterization test benchSystems Design Engineering

Staff Systems Design Engineer

Nov 2005Mar 2009 · 3 yrs 4 mos · Bengaluru, India

  • # Responsible for complete design and silicon performance characterization/productization of
  • AGC/Carrier sense/Freq-Est/Timing synchronization/PHY Packet FSM modules of a 1st generation low
  • power WLAN+BT 1x1 11n receiver
  • ## Worked on implementing common AGC/medium access/Finite State Machine based priority
  • algorithms between WLAN, BT RF front-ends to improve coexistence system performance
  • ## This is the 1st BRCM chip to fetch >2B$ revenue
  • ## Worked on multiple top mobile customer product design platforms under hectic deadlines
Design and silicon performance characterizationAGC/Carrier sense/Freq-Est algorithmsWLAN Systems DesignTelecommunications

Athena semiconductors, bangalore ( acquired by broadcom , usa in 2005)

DSP Engineer

Oct 2004Nov 2005 · 1 yr 1 mo · Bengaluru, India

  • # Worked on optimizing area/power of efficient LDPC/Viterbi decoding algorithms targeted for a 2x3
  • WLAN system
  • # Worked on enhanced MF/Auto-Corr based carrier detection algorithms to improve receive sensitivity
  • for a 2x3 WLAN system.
  • # Worked on wireless system level debugging of first generation legacy 802.11a/b/g chip set using
  • performance analysis tools like Chariot/Airopeek/real time FPGA platform to troubleshoot various
  • real world PHY/RF interface issues
LDPC/Viterbi decoding algorithmsCarrier detection algorithmsWireless Systems DesignTelecommunications

Education

National Institute of Technology Calicut

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2000Jan 2004

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