Rishikesh V Pai

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in SoC architecture and RTL design.
Holds a USPTO patent on test-time reduction.
Proficient in Cadence Palladium emulation environments.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC architecture and verification.

Contact

Skills

Core Skills

Soc ArchitectureRtl Design & SynthesisDft

Other Skills

Performance modellingApplication-Specific Integrated Circuits (ASIC)Cadence Palladium EmulationVerificationPerformance AnalysisRTL DesignPerlComputer ArchitectureSystem on a Chip (SoC)ScriptingDebuggingShell ScriptingVerilogComputer SimulationsVLSI

About

Digital design engineer with 4+ years at Texas Instruments, working across SoC architecture, front-end RTL design and synthesis, and Design For Testability on ARM-based MCU-class devices. I've worked on CPU subsystem performance analysis, memory subsystem architecture, Cadence Palladium emulation environments for multi-core SoC benchmarking, and end-to-end structural verification through to post-silicon debug. I also hold a USPTO patent on test-time reduction.

Experience

3 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

3 yrs 11 mos

Current Experience

Texas instruments

3 roles

Digital Design Engineer

Jul 2022 – Present · 3 yrs 11 mos

SoC Architecture:
Cadence Palladium Emulation: Brought up emulation environments to run real-world workloads across multi-core SoCs at near-silicon speeds, enabling system-level benchmarking and performance characterisation pre-silicon.
Architecture & Performance: Bottleneck analysis and benchmarking for ARM R-class and M-class CPU subsystems. Redesigned memory subsystem to reduce access latency — increased controller throughput and repositioned pipeline stages for optimised handling.
Hardware Accelerator Design: Modelled and analysed a hardware accelerator datapath for edge AI inferencing. Wrote RTL and drove front-end synthesis to determine optimal pipeline stages and datapath topology, evaluating area, power and throughput trade-offs.
DFT & Verification:
Owned end-to-end structural verification for an SoC: test generation, fault-model coverage, silicon bring-up and post-silicon debug.
JTAG-based functional verification of the DFT subsystem.
USPTO patent on test-time reduction.

Performance modellingApplication-Specific Integrated Circuits (ASIC)SoC ArchitectureCadence Palladium EmulationDFTVerification+1

Digital engineering intern

Jan 2022 – Jun 2022 · 5 mos

Developed Python and TCL scripts to automate test generation and RTL generation workflows within the scope of DFT, reducing manual EDA tool interaction and iteration time.

DFTPerl