A

Ayush Mehrotra

Director of Engineering

Uttar Pradesh, India16 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI digital design implementation.
Director at Cadence with a focus on PPA methodology.
Extensive experience in physical design and verification.

Stackforce AI infers this person is a VLSI design expert specializing in digital design and application engineering.

Contact

Skills

Other Skills

TCLPhysical DesignEDAStatic Timing AnalysisICCTalusLogic SynthesisSignal IntegrityIntegrated Circuit DesignRTL designVLSILow-power DesignTiming ClosureSoCPhysical Verification

About

VLSI Professional with ability to work in Digital Design Implementation including: • Floorplanning • Power planning • Physical Implementation • Clock Tree Synthesis • Routing

Experience

16 yrs 1 mo

Total Experience

3 yrs 2 mos

Average Tenure

7 yrs 11 mos

Current Experience

Cadence

4 roles

Director of Application Engineering

Promoted

Jan 2026 – Present · 5 mos

Sr Principal Application Engineer

Jul 2022 – Jan 2026 · 3 yrs 6 mos

Principal Application Engineer

Promoted

Oct 2020 – Jul 2022 · 1 yr 9 mos

Lead Sales Application engineer

Apr 2018 – Jul 2020 · 2 yrs 3 mos · Noida, Uttar Pradesh, India

Mentor graphics

Senior Application Engineer

Jun 2013 – Apr 2018 · 4 yrs 10 mos · Bangalore

Synopsys

Application Engineer

Mar 2012 – Jun 2013 · 1 yr 3 mos · Bangalore

Magma design automation

Associate Application Engineer

Mar 2011 – Mar 2012 · 1 yr · Bangalore

Planetcast international

Network Engineer

Feb 2010 – Mar 2011 · 1 yr 1 mo

Stackforce found 100+ more professionals with TCL & Physical Design

Explore similar profiles based on matching skills and experience

Senthil Kumar Murugaiah

Sr. Manager Silicon Design Engineering

at AMD

Hyderabad, India25 yrs 8 mos exp

Product ManagementEngineering Management

Sreekanth Billupati

Digital Design Engineer

at C2i Semiconductors

Sri Potti Sriramulu Nellore, India6 yrs 11 mos exp

Product Design5G New Radio (NR)Team Leadership

Devesh Prajapat

Analog Circuit Design Engineer II

at Cadence

Bikaner, India3 yrs 4 mos exp

Mixed-Signal IC DesignAnalog Integrated Circuit DesignDigital Circuit Design

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp

Integrated Circuit DesignPhysical Design

Basannagouda Reddy

Director R&D

at Synopsys Inc

San Francisco, United States23 yrs 2 mos exp

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp

SRAMLibrary ValidationComponent DesignPDK ValidationSimulation

Ajosh Kunnummal Jose

Senior Staff Design Engineer

at Infineon Technologies

Bengaluru, India15 yrs 11 mos exp

Power and IR/EM AnalysisVoltusPhysical VerificationIR drop analysisReliability verification

Anand Bhujade

Senior Design Engineer

at Qualcomm

Nagpur, India5 yrs 6 mos exp

ASIC DesignVLSI DesignDesign verification