Waris Quraishi

Software Engineer

Delhi, India5 yrs 2 mos experience

Key Highlights

Experienced in RTL Design and UVM methodologies.
Proficient in multiple programming languages including Python and C++.
Currently a Staff Engineer at Synopsys Inc.

Stackforce AI infers this person is a highly skilled engineer in the semiconductor and digital design industry.

Contact

Skills

Core Skills

Rtl DesignUniversal Verification Methodology (uvm)

Other Skills

Validation ProtocolDigital DesignsLinuxSystemVerilogTCLEthernetPython (Programming Language)C (Programming Language)C++Verilog

Experience

5 yrs 2 mos

Total Experience

2 yrs 11 mos

Average Tenure

2 yrs 2 mos

Current Experience

Synopsys inc

2 roles

Staff Engineer

Promoted

Apr 2026 – Present · 2 mos

RTL DesignValidation ProtocolDigital DesignsLinuxUniversal Verification Methodology (UVM)SystemVerilog+6

Solutions Engineer 2

Apr 2024 – Present · 2 yrs 2 mos

X-epic

2 roles

R&D Engineer 2

Promoted

Jan 2023 – Mar 2024 · 1 yr 2 mos

Engineer 1

Feb 2021 – Dec 2022 · 1 yr 10 mos

Dkop labs pvt. ltd.

Trainee

Jan 2019 – Sep 2020 · 1 yr 8 mos

Education

Dr. A.P.J. Abdul Kalam Technical University (AKTU), Lucknow

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Stackforce found 100+ more professionals with Rtl Design & Universal Verification Methodology (uvm)

Explore similar profiles based on matching skills and experience

Gomita Ravanavar

Talent Acquisition Specialist

at AVEVA

Bengaluru, India9 yrs 3 mos exp

Talent AcquisitionRecruitment ManagementSales ManagementMarketing

Abhay Gautam

Staff R&D Engineer

at Synopsys Inc

Noida, India4 yrs 5 mos exp

CVerification

Soobin Kim

Software Engineer

at Synopsys Inc

Seoul, South Korea4 yrs exp

SoCHardware Emulation

Erik Zatikyan

Analog and Mixed Signal Senior Engineer

at Synopsys Inc

Yerevan, Armenia4 yrs 1 mo exp

Analog Circuit Design

Piyush Sukhija

Applications/Sales Engineering , Sr. Director

at Synopsys

Reading, United Kingdom20 yrs 4 mos exp

Functional VerificationCustomer RelationsFPGASOC

Jayesh Salve

Accumulated Expertise

at Career-Wide Experience

Navi Mumbai, India0 mo exp

Rajendra Kumar

Software Architect

at Cadence Design Systems

Noida, India21 yrs 7 mos exp

SystemVerilogEDABehavioral synthesisC++ASIC

Sanjay Goyal

Application Engineer (Physical Design)

at Cadence Design Systems

Noida, India9 yrs 2 mos exp

Physical DesignPlace & Route