Murugesan R

VP of Engineering

India25 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led 38 successful tape outs with first pass success.
Mentored over 80 engineers in analog circuit design.
Expert in SerDes interfaces and mixed-signal IC development.

Stackforce AI infers this person is a highly skilled technical leader in the semiconductor industry with expertise in analog and mixed-signal IC design.

Contact

Skills

Core Skills

Analog Circuit DesignEngineering ManagementSerdesAms VerificationIp DesignTeam Management

Other Skills

High Speed IPsAnalog IPsUSB4TBT3PCIe5.0Protocol complianceCertificationAnalog IP DevelopmentTurnkey ProjectsMIPI DPHY14nm Technology10nm TechnologyCircuit DesignTransmitter DesignLPDDR3/4

About

Task-oriented Technical leader and Engineering manager of advanced Analog & mixed-signal ic developments - from definition of the initial Concept, Architectural analysis & selection, Specification, Circuit design, Layout supervision, Lab debug & Circuit verification & Validation. Completed over 38 tape outs with first pass success. Driven by project success and the success of the Team, Mentored/Trained more 80 engineers in the art of Analog/Mixed signal circuit design and layout. Combines the technical and project leadership/customer facing functions for brand-new architectures where the development path is both risky and technically uncharted. Lead Terminus circuits design & layout team , it is a state-of-the-art mixed-signal IC development in Bangalore. Previously led Intel Display port team development in 32/7nm to working silicon and inclusion and also led Microchip & Motorola analog design team. Experienced Technical Leader across Multi-National sites (US, Singapore, Germany, Thailand and Malaysia ). Deep expert in SerDes interfaces, data transmission, analog CMOS design and the 'physical layer' commonly. Specialties:Analog CMOS Design Mixed Signal CMOS design SerDes Physical Layer Interfaces Transmitters Receivers SAR ADCs PLLs ( LC & RO) LDOs SRAM Circuit Verification & Lab Validations

Experience

25 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

5 yrs 8 mos

Current Experience

– Present

Sykatiya technologies private limited

Vice President of Engineering

Oct 2020 – Present · 5 yrs 8 mos · Bengaluru, Karnataka, India

Leading the development of High Speed IPs and complex analog IPs, driving innovation and meeting customer requirements.
Built and managing a strong analog design team, supporting Turn key and customer programs at SYKATIYA TECHNOLOGIES PRIVATE LIMITED.

High Speed IPsAnalog IPsTeam ManagementAnalog Circuit DesignEngineering Management

Granite river labs inc.

Senior Design Consultant (High speed SerDes)

Sep 2019 – Oct 2020 · 1 yr 1 mo · Bengaluru

worked on USB4 , TBT3 and PCIe5.0 IP integration for the Protocol compliance and certification

USB4TBT3PCIe5.0Protocol complianceCertificationSerDes+1

Tech mahindra cerium pvt ltd

Architect (SerDes design and AMS Verification)

Mar 2017 – Sep 2019 · 2 yrs 6 mos · Bangalore

Analog and SerDes IP Development
Managing small Analog Deisgn, Layout and AMS verification Team
Design porting and handling turnkey projects @ lower nodes (TSMC 7nm)
MIPI DPHY 1.2 development in 14nm and 10nm process technology
Overall Lead and managing Circuit, Layout, RTL, Verification, SD and IP release Team.

Analog IP DevelopmentAMS VerificationTurnkey ProjectsSerDesAnalog Circuit Design

Invecas

Analog IP Design Lead

Nov 2015 – Mar 2017 · 1 yr 4 mos · Hyderabad Area, India

I was working as circuit design manager for the Circuit Design Development group and taking responsibility of designing Transmitter for the LPDDR3/4 and DDR3/4 cutting edge technology ( 14nm and 22FDSOI Process Technology).

Circuit DesignTransmitter DesignLPDDR3/4Analog Circuit DesignIP Design

Terminus circuits pvt ltd

Technical Lead (SerDes, Analog IPs)

Jan 2013 – Nov 2015 · 2 yrs 10 mos · Bangalore

I was managing 20 members Design Team ( 8 member Analog/Circuit Designers, 6 members Layout Team and 3 members Digital Design Team and 2 members AMS Verification Team). Taking care of overall Circuits Design, Simulations, Layout, and Floor Planning, Pre-silicon & Post-silicon validations, supervision of Design, Layout, Digital and AMS design activities. Conducting regular design, layout review and preparing design documents for the future requirements.
Other responsibilities like Preparing Specifications datasheet, project proposal, Preparing Product/IP Datasheet, Customer interaction, and IP delivery. Also taking care of Testchip shuttle preparation to decide the bump/pin requirements, SOC integrations and Tapeouts.
Our PHY/PMA is targeted for the server, Enterprise and PC applications. PHY will be developed by our internal team and will be integrated for the SOC product developments where PCS and Controller from different vendors.

Circuit DesignLayout SupervisionPre-silicon ValidationAnalog Circuit DesignTeam Management

Intel corporation

Senior Component Design Engineer

Jun 2009 – Dec 2012 · 3 yrs 6 mos · Bangalore

I was part of Display port design team. Worked on high frequency PLL developments( 5.4GHz), Transmitter design, Receiver design, Bias designs and LDOs which can support low power mode requirements, FEV exectuion lead, Display port IP execution Lead ( Techincal Lead) 4 to 7 members team.

PLL DevelopmentTransmitter DesignReceiver DesignAnalog Circuit DesignEngineering Management

Microchip technology inc.

Principal Analog Design Engineer

Sep 2004 – Jun 2009 · 4 yrs 9 mos · Bangalore,India

I was Analog Design lead where my contributions are design and execution of SAR ADCs, Analog PLLs, LVDS, POR, BOR, voltage Regulators, 16-32bit Microcontroller, Charge pump circuits, (32K- 8MHz) Oscillators, Spread Spectrum PLLs, SRAMs and trainings for the factory peoples (working on testing, validation and FAE support) also closely worked with marketing teams.

SAR ADCsAnalog PLLsVoltage RegulatorsAnalog Circuit DesignIP Design