D

Dileep Airani R .

Software Engineer

Bengaluru, Karnataka, India5 yrs 4 mos experience
Highly Stable

Key Highlights

  • 4+ years of experience in DFT engineering.
  • Proficient in SCAN and ATPG methodologies.
  • Basic knowledge of MBIST and JTAG technologies.
Stackforce AI infers this person is a DFT Engineer with expertise in test methodologies and design for testability.

Contact

LinkedIn

Skills

Core Skills

DftScan

Other Skills

DFT insertionJoint Test Action Group (JTAG)TCLFusion CompilerOCCmbistijtagjtagTessentAutomatic Test Pattern Generation (ATPG)Pattern simulationCoverage Improvement

Experience

5 yrs 4 mos
Total Experience
4 yrs 4 mos
Average Tenure
11 mos
Current Experience

Aritrak technologies private limited

DFT Engineer

Jul 2025 – Present · 11 mos · On-site

  • DFT Engineer
DFTSCAN

.

DFT Engineer

Feb 2021 – Jul 2025 · 4 yrs 5 mos · On-site

  • DFT Engineer

Stackforce found 100+ more professionals with Dft & Scan

Explore similar profiles based on matching skills and experience

DP

Devesh Prajapat

Analog Circuit Design Engineer II

at Cadence

Bikaner, India3 yrs 4 mos exp
Mixed-Signal IC DesignAnalog Integrated Circuit DesignDigital Circuit Design
Subrata Roy

Subrata Roy

Director

at NVIDIA

Bengaluru, India25 yrs 1 mo exp
EDADFTC++HDLFPGA
Pradeep Korada

Pradeep Korada

Associate

at PwC India

Srikakulam, India3 yrs 9 mos exp
Embedded SystemsFirmware
S Thimothy

S Thimothy

Software Engineer

at HCLTech

Hubli-Dharwad, India1 yr 3 mos exp
Design AutomationVLSISilicon ValidationHardware EngineeringRTL Design
Nilam Sachan

Nilam Sachan

Senior Manager R&D

at Synopsys Inc

Noida, India22 yrs 10 mos exp
Product DevelopmentProject ManagementArchitectural DesignDFTTechnical Leadership
Shivani Kapoor

Shivani Kapoor

RTL Design Engineer

at NVIDIA

San Francisco, United States8 yrs 2 mos exp
RTL DesignComputer ArchitectureTeam LeadershipDigital IC DesignSoC Design
AK

Ajith Kumar R

STA Engineer

at Marvell Semiconductor

Bengaluru, India8 yrs 1 mo exp
STA EngineeringTiming Closure
VP

VENKATA JAGADISH PEDIREDLA

Embedded system R&D Engineer

at Avyantra

East Godavari, India1 yr exp
Design-for-Testability (DFT)VLSI TestingRTL DesignVLSI DesignEmbedded System Design