Mahesh Parmar

Product Manager

Bengaluru, Karnataka, India15 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in formal verification methodologies for high-speed interconnects.
Led development of AMBA CHI protocol Assertion IP.
Strong background in complex datapath verification.

Stackforce AI infers this person is a Formal Verification Engineer specializing in ASIC and high-speed interconnect protocols.

Contact

Skills

Core Skills

Formal VerificationHigh-speed InterconnectsAmba Chi Protocol

Other Skills

SystemVerilog AssertionsDeadlock DetectionData Integrity VerificationSoC Connectivity ChecksFPVDatapath VerificationTclPerlNetwork PlanningRadio Frequency TestsMobile Switching Center MaintenanceVerilogVCSCoveragesRegression Testing

About

Experienced Senior Application Engineer with a demonstrated history of working in the computer software industry. Skilled in SystemVerilog, Application-Specific Integrated Circuits (ASIC), Formal verification, Datapath verification, Assertion IP developer. convergence debug, AMBA protocol expert. Strong engineering professional graduated from Birla Institute of Technology and Science, Pilani.

Experience

15 yrs 4 mos

Total Experience

5 yrs 3 mos

Average Tenure

4 yrs 9 mos

Current Experience

Amd

Senior Member of Technical Staff

Sep 2021 – Present · 4 yrs 9 mos · Bangalore Urban, Karnataka, India

Formal Verification Engineer – High-Speed Interconnects
Specialize in verifying complex high-speed interconnect protocols using formal verification methodologies.
Expert in handling design complexity through abstraction techniques, symbolic model execution, and state space reduction.
Skilled in ensuring forward progress, liveness, and safety properties in interconnect fabrics.
Experienced in building scalable formal testbenches, leveraging SVA (SystemVerilog Assertions), abstraction models (queues, memory, arbiters).
Strong background in deadlock/livelock detection, ordering rules, and data integrity verification for on-chip and system-level interconnects.

Formal VerificationHigh-Speed InterconnectsSystemVerilog AssertionsDeadlock DetectionData Integrity Verification

Synopsys inc

Staff FV Engineer

Aug 2012 – Sep 2021 · 9 yrs 1 mo · Bengaluru

Developer and owner of latest AMBA CHI protocol Assertion IP development
Primary owner of AIP development for a potential Synopsys account
Working with multiple teams within Synopsys as a Formal verification lead to sign off various designs
I have exhaustive experience in formal verification that mainly includes
SoC connectivity checks.
FPV for complex packet based designs
Unreachability analysis for coverage closure at IP level and Soc level.
Sequential equivalence checking for clock gating, re-timing.
Datapath verification. Verified complex CPU instructions with 4k wide inputs, complex multipliers
Register Verification
Knowledge and strong debug skill of AMBA AHB, AXI, APB, ATB and CHI protocols.
Good hands on automating processes using tcl and perl.