DILEEP CHANDRASEKHARAN P

Software Engineer

Bengaluru, Karnataka, India6 yrs 10 mos experience
Highly Stable

Key Highlights

  • 5 years of experience in IP & SoC Verification.
  • Expertise in DDR projects at AMD and Intel.
  • Strong knowledge in UVM, SystemVerilog, and Verilog.
Stackforce AI infers this person is a VLSI Verification Engineer with a focus on DDR technologies.

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Skills

Core Skills

Functional Verification

Other Skills

DDR Functional ValidationDDRUniversal Verification Methodology (UVM)SystemVerilogAssertionsConstraints and RandomizationCode CoverageCoverageAnalytical SkillsSystem on a Chip (SoC)DebuggingEngineeringMicrosoft OfficeInterpersonal CommunicationRTL Design

About

~5 Years of experience in DV. Familiar with IP & SoC Verification. Worked on multiple DDR Projects in AMD & INTEL. Worked on Coverage, Assertions, Clock and Critical Signal Checkers. Sound knowledge in UVM, SystemVerilog, Verilog. Knowledge in DDR5, LPDDR5, LPDDR6, AMBA AHB, APB Protocols. "Reading this won't help you...Don't waste your time" It was in early 2000s. I was in 3rd or 4th standard and I had the habit of reading comics. One day when I was keenly reading some comic books, one of my relatives told me this. Those comics not only contains fun but also facts and features. Articles on world classic movies and life lessons of great personalities that gave me an exposure to the world. Among those, I was fascinated by the stories of scientists, engineers and movies related to college life. All of these ignited a passion for Engineering in me. The residential schooling system (Jawahar Navodaya Vidyalaya) moulded me to adapt to situations and improved my confidence. It taught me to be more human. It taught me to go for what I want. And after completion of the course, I went for it. As always, the initial phase was the toughest. Being a Science student with Biology as the only option in school, I was troubled by C programming. Gradually we became friends. But I met my besties in later semesters. VLSI was such a nice partner. I developed emotions for it and I decided not to leave its side. And that's how I became a Post Graduate scholar in Micro and Nano Electronics after clearing GATE 2019 with a score of 492. Delving into the core of VLSI, I enjoyed the pain. The strong desire to work in VLSI helped me to reject the job offer from an IT MNC. And yes, I believe in VLSI. I believe in myself. I believe that nothing is useless. Every book you read, every act you do, every gesture you make matters... So let's connect... It matters...

Experience

6 yrs 10 mos
Total Experience
2 yrs 10 mos
Average Tenure
1 yr 2 mos
Current Experience

Intel corporation

IP Design Verification Engineer

Apr 2025Present · 1 yr 2 mos · Bengaluru, Karnataka, India

  • Working on DDR Functional Validation
DDR Functional ValidationFunctional Verification

Amd

Design Verification Engineer

Sep 2024Apr 2025 · 7 mos · Bengaluru, Karnataka, India · Hybrid

  • Worked on DDR.
DDRFunctional Verification

Nvidia

Design Verification Engineer

Apr 2022Apr 2024 · 2 yrs · Bengaluru, Karnataka, India · Hybrid

  • Worked on SOC Verification
Functional VerificationAssertions

L&t technology services limited

Design Verification Engineer

Aug 2021Apr 2025 · 3 yrs 8 mos · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilogFunctional Verification

College of engineering, trivandrum

Post Graduate Scholar

Aug 2019Aug 2021 · 2 yrs · Trivandrum, Kerala, India

SystemVerilog

Education

College of Engineering Trivandrum

Master of Technology - MTech — MICRO AND NANO ELECTRONICS

Aug 2019Sep 2021

Government Engineering College, Thrissur

Bachelor of Technology - BTech

Aug 2014Jun 2018

Jawahar Navodaya Vidyalaya - JNV

Jun 2006Mar 2013

Government Engineering College, Thrissur

Bachelor of Technology - BTech

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