Adarsham Jha

Software Engineer

India2 yrs experience
Most Likely To Switch

Key Highlights

  • Expert in Analog Mixed Signal Verification.
  • Proficient in System Verilog and Formal Verification.
  • Strong foundation in VLSI and Digital Logic design.
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in Analog Mixed Signal and Formal Verification.

Contact

LinkedIn

Skills

Core Skills

System VerilogFormal Verification

Other Skills

System Verilog AssertionsUnixJasperSQLVerilog-AMSVerilog-ADigital LogicDigital DesignsLinuxComputer-Aided Design (CAD)CAD ToolsVerilogVHDLInformatica PowerCenterPython (Programming Language)

Experience

2 yrs
Total Experience
1 yr
Average Tenure
1 yr 9 mos
Current Experience

Renesas electronics

2 roles

AMS Verification Engineer

Promoted

Apr 2025 – Present · 1 yr 2 mos

AMS Verification Associate Engineer

Sep 2024 – Apr 2025 · 7 mos

System VerilogSystem Verilog Assertions

Synopsys inc

Validation Engineer

Jun 2024 – Sep 2024 · 3 mos · Hyderabad, Telangana, India · Remote

  • Sub-contractor

Stmicroelectronics

Formal Verification

Jun 2023 – Jun 2024 · 1 yr · Greater Noida · On-site

UnixJasperFormal Verification

Cognizant

Intern

Jan 2022 – May 2022 · 4 mos

SQL

Education

Thapar Institute of Engineering & Technology

Master of Technology - MTech — VLSI

Aug 2022 – Aug 2024

Haldia Institute of Technology

Bachelor of Technology - BTech

Jan 2018 – Jan 2022

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