MADDALI YASWANTH — Software Engineer

I am a Senior ASIC Digital Verification Engineer with hands-on experience in building and maintaining UVM-based verification environments for complex PCIe and multi-protocol subsystems. My expertise spans SystemVerilog, UVM, and formal verification, with strong exposure to APB, AXI, AHB, and PCIe protocols, including dual-mode and PHY-only designs. In my current role, I work on large-scale subsystem verification, developing reusable UVM agents, drivers, monitors, sequencers, and scoreboards, and validating DUT-level functionality against detailed specifications. I have contributed to multiple PCIe projects, executing comprehensive scenarios such as enumeration, link training, error handling, speed changes, FLR, SR-IOV, and PF/VF configurations, while ensuring protocol compliance and stability. I also apply formal verification using VC Formal for connectivity and protocol checks, collaborate closely with design teams through VPLAN reviews, and perform structured debug using VCS and waveform analysis. Academically, I hold a Master’s degree in VLSI Design and have published IEEE conference papers in neural networks. My work includes FPGA-based neural network implementation in Verilog and low-power digital circuit design projects, reflecting my interest in combining hardware verification, architecture, and intelligent systems. I am passionate about contributing to high-performance silicon and hardware development teams and continuously advancing my expertise in ASIC verification and SoC design.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and SoC design.

Location: Hyderabad, Telangana, India

Experience: 3 yrs