Jeegar Bakhai

Associate Partner

Bengaluru, Karnataka, India24 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in Performance Analysis and Stakeholder Management.
  • Proven track record in Firmware and Validation Engineering.
  • Leadership in driving innovations in Semiconductor industry.
Stackforce AI infers this person is a Semiconductor industry expert with strong leadership in performance analysis and validation engineering.

Contact

Skills

Core Skills

Performance AnalysisStakeholder ManagementFirmware DevelopmentPost-silicon ValidationValidation EngineeringSoftware Development

Other Skills

Data ScienceCustomer RelationshipsArm ArchitectureFPGAsWeb Application DevelopmentCUEFIACPIC++PythonAssemblyPerlSpecmanMicroarchitectureTcl

About

Extensive experience in the Semiconductor Industry, managing and leading multiple functions including Performance Analysis, Post-Silicon Validation, Pre-Silicon Validation, Firmware Development and Software Development.

Experience

24 yrs 1 mo
Total Experience
14 yrs 1 mo
Average Tenure
1 yr 5 mos
Current Experience

Mips

Senior Director Performance at MIPS

Jan 2025Present · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

Arm

Principal Performance Analysis Engineer

Jun 2016Present · 10 yrs · Bengaluru, Karnataka

  • Managing and providing Technical Leadership to Performance Analysis Team working on Arm Core IP.
  • Managing Stakeholders from multiple Lines of Business including Client, Server, Automotive, IOT and Machine Learning.
  • Representing Arm Performance Analysis function at Customer Meetings and building direct relationships with Customers.
  • Driving various innovations including usage of Data Science in Predicting Benchmark Scores, FPGAs usage for runtime reduction, Web Application for Performance Dashboard.
  • Acquired expertise in People Management, Performance Analysis, Arm Architecture, Customer Relationships, Stakeholder Management and Planning.
Performance AnalysisData ScienceStakeholder ManagementCustomer RelationshipsArm Architecture

Intel corporation

4 roles

Senior Firmware Engineer

Jul 2014Jun 2016 · 1 yr 11 mos

  • Owned delivery of Graphics Bios for All Intel Tablet and Netbook products.
  • Drove development of Platform and Graphics Bios for latest generation Atom processor for Chromebooks and Netbooks.
  • Acquired expertise in C, UEFI and ACPI.
CUEFIACPIFirmware Development

Post Silicon Validation Engineer

Feb 2008Jul 2014 · 6 yrs 5 mos

  • Owned Validation of Mission Critical Components of Server CPUs.
  • Owned Delivery of RIT tool for Cache Coherency Validation of Server CPUs.
  • Delivered Validation Tools Critical for successful launches of several Server CPUs.
  • Drove Optimization of Validation Infrastructure leading to 30% improvement in Validation Throughput.
  • Acquired expertise in C++, Python and Assembly.
C++PythonAssemblyPost-Silicon Validation

Validation Engineer

Promoted

Dec 2004Feb 2008 · 3 yrs 2 mos

  • Owned Validation of DFX and DFD features on Itanium server CPUs.
  • Delivered Robust Debugging Infrastructure to Server OEMs.
  • Acquired expertise in C++, Perl, Assembly, Specman and Microarchitecture.
C++PerlAssemblySpecmanMicroarchitectureValidation Engineering

Software Developer

May 2002Dec 2004 · 2 yrs 7 mos

  • Developed leading-edge techniques for Co-Simulation of CPU and Chipset.
  • Developed Robust Testing Infrastructure for Co-Simulation testing that was used on Itanium and Xeon CPUs.
  • Acquired expertise in Perl, Tcl and Microarchitecture.
PerlTclMicroarchitectureSoftware Development

Education

Georgia Institute of Technology

BS — Computer Engineering

Jan 1998Jan 2002

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