Feb 2026 – May 2026 · 3 mos · Noida · On-site

Jul 2024 – Jan 2026 · 1 yr 6 mos · Noida · On-site

• Led pre-silicon verification of PCIe4 PHY IP, validating its functionality in UVM-based reusable verification environments, (PCIe IP , UVM)
• Enhanced assertion-based verification (SVA) by refining and adding assertions, directly from the protocol spec. , achieving 100% assertion coverage: (SV, Assertions (SVA))
• Executed and analyzed multi-configuration regressions, performed root-cause analysis, raise jira for issue and collaborated with RTL teams to resolve design and testbench issues : (REGRESSION, Debugging, UVM,
• SV)
• Defined verification strategy and contributed to test plan development, ensuring comprehensive coverage of PCIe IP features and corner cases: (Testplan/Verification Plan)
• Experience in leveraging AI/ML-driven verification tools (VSO.ai) to accelerate coverage closure and regression efficiency.: (Automation, AI/ML-Driven Verification)
• Owned coverage-driven verification, improving overall functional and code coverage from 70% to 90%
• through systematic analysis of coverage gaps, targeted test enhancements, and assertion strengthening.
• Developed automation to figure out the tests that targets the changed code and code affected by those changes accelerating debug cycles : (Automation)
• Optimized regression strategy by analyzing redundancy and coverage overlap, reducing regression test count by 30% while maintaining functional and code coverage : (Regression Optimization)
• Deployed DTL technology on PCIe IP by restructuring the UVM Testbench env. into packages , to avoid recompiling design and sumulating base test again and again, enabling faster execution of extended tests
• Implemented DUT Root Cause Analysis (DUT-RCA) to trace simulation mismatches back to faulty RTL or testbench logic. : (Debugging)
• Created unit-level reproducers from IP failures for effective JIRA filings , accelerating debug and collaborated closely with RTL and R&D teams to validate fixes.: (System Verilog (SV))

Jun 2023 – Jul 2024 · 1 yr 1 mo · Delhi, India · On-site

• Pursuing training in Design and verification domain. Practical knowledge of Front-end VLSI design and
• Verification techniques. The training includes Digital Electronics, STA, CDC, Verilog, System Verilog,
• UVM ,C/C++ ,Linux and hands-on projects.