Rajnish Kumar — Product Engineer
Design Verification Engineer. Well versed with Formal Verification and simulation. UVM SV ASSERTIONS
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and electronic design automation.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 10 mos
Skills
- Rtl Verification
- Digital Designs
Career Highlights
- Expert in Formal Verification and simulation techniques.
- Proficient in Universal Verification Methodology (UVM) and SystemVerilog.
- Strong background in RTL and Functional Verification.
Work Experience
Renesas Electronics
Design Verification Engineer (1 yr 4 mos)
Synopsys Inc
Formal verification Trainee (7 mos)
DXCorr Design Inc
RTL Design Engineer (6 mos)
STMicroelectronics
Design verification Intern (10 mos)
Education
M.Tech at Indian Institute of Technology, Patna