Tapan Halder

Director of Engineering

San Jose, California, United States35 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in advanced verification and simulation technology.
Achieved 5×–10× simulation gains in R&D.
Led cross-functional collaboration for high-performance deployment.

Stackforce AI infers this person is a leader in EDA with expertise in verification and simulation technologies.

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Skills

Core Skills

Verification And Validation (v&v)SimulationSoftware DevelopmentSynthesis

Other Skills

Mixed SignalLow Power VerificationVerificationSimulation ArchitectureSimulation accelerationVerification methodologiesDebug environmentMixed-signal designMicrosoft PowerPointC (Programming Language)VHDLSimulation performanceC++Synthesis subset checkSystemVerilog

Experience

35 yrs 10 mos

Total Experience

11 yrs 11 mos

Average Tenure

Current Experience

Synopsys inc

Senior Director, R&D

Dec 1997 – Jan 2026 · 28 yrs 1 mo · Mountain View, CA, USA · On-site

Senior R&D Director specializing in advanced verification and simulation technology, recognized for driving transformative innovation and sustained market leadership. Spearheads strategic R&D initiatives and platform evolution, achieving significant revenue growth through pioneering performance breakthroughs. Expert in simulation acceleration, verification methodologies, debug environment, low power verification and mixed-signal design, delivering 5×–10× simulation gains and enhancing competitive advantage. Champions cross-functional collaboration, ensuring seamless integration and high-performance deployment across hyperscaler environments. Expert in hardware assisted simulation performance, AI/ML for EDA, Software engineering methodology, product development from concept to productization to deployment at customer end.

Mixed SignalLow Power VerificationVerificationSimulation ArchitectureVerification and Validation (V&V)Simulation

Viewlogic

Principal Engineer

Mar 1996 – Dec 1997 · 1 yr 9 mos · Fremont, CA · On-site

Principal developer for Vantage VHDL Simulator for all front end, elaboration and code generation work. Improved elaboration time by up to 6x and improved core simulation performance by 2X.

Microsoft PowerPointC (Programming Language)Software DevelopmentSimulation

Cadence design systems

SMTS/Project Lead

Jan 1989 – Jan 1995 · 6 yrs · Noida · On-site

Integrated the Leapfrog VHDL front end for Synergy - first generation Synthesis tool from Cadence. Added all Synthesis subset check.
Contributed to the Vital timing checks for VHDL simulator.
Project lead and developer for the EDIF300 tool from concept to deployment.

C++VHDLSoftware DevelopmentSynthesis