Sudhanshu Gulavani

Software Engineer

Bengaluru, Karnataka, India4 yrs experience
Highly Stable

Key Highlights

  • Expert in standard cell characterization across multiple technology nodes.
  • Hands-on experience with Cadence tools and automation scripting.
  • Strong foundation in VLSI design and mixed-signal workflows.
Stackforce AI infers this person is a Microelectronics expert with a focus on VLSI design and automation.

Contact

Skills

Core Skills

Standard CellCharacterizationVery-large-scale Integration (vlsi)Analog Integrated Circuit Design

Other Skills

Standard Cell CharacterizationAutomation ScriptsLibrary DesignMATLABAnalog Circuit DesignAutomation FlowsShell ScriptingMicroelectronicsVerilogPython (Programming Language)Internet of Things (IoT)Cadence VirtuosoSPICELTSpiceMachine Learning

About

I completed my M.Tech in VLSI Design from NIT Durgapur, where I built a strong foundation in semiconductor devices, circuit design, and EDA flows. This academic journey gave me hands-on exposure to Cadence tools and scripting, strengthening both my design and problem-solving skills. I gained practical industry experience during my research internship at IISc Bangalore, working on digital synthesis, place & route, and analog design flows. My work included implementing gm/ID-based analog methodologies in MATLAB and circuit/layout design in Virtuoso, which deepened my understanding of mixed-signal workflows and advanced design practices. Currently, I work as a Senior R&D Engineer at Synopsys, Bangalore, specializing in standard cell characterization across multiple technology nodes. I deliver high-quality libraries (NLDM, CCS, LVF, OCV), develop automation scripts in Python and Shell, and enhance QA frameworks and characterization methodologies. My focus is on driving efficiency, accuracy, and scalability in library design — enabling faster, more robust semiconductor development.

Experience

4 yrs
Total Experience
4 yrs
Average Tenure
4 yrs
Current Experience

Synopsys inc

3 roles

R&D Staff Engineer

May 2026Present · 1 mo

Standard Cell CharacterizationAutomation ScriptsLibrary DesignStandard CellCharacterization

Senior Research And Development Engineer

Promoted

Jan 2024May 2026 · 2 yrs 4 mos

Very-Large-Scale Integration (VLSI)Characterization

R&D Engineer II

May 2022Dec 2023 · 1 yr 7 mos

Indian institute of science (iisc)

Intern

Jun 2021Jun 2022 · 1 yr · Dombivli, Maharashtra, India

  • >The research work involves rapid analog design for machine learning architectures at edge.
  • >Developing automation flows for end to end VLSI design flow for mixed signal design.
  • >Using a new approach in analog circuit design using Matlab lookup tables and trans-conductance efficiency as an approximation.
  • >Python based environment for remote hardware testing and equipment control.

Education

National Institute of Technology Durgapur

Master of Technology - MTech — vlsi

Jan 2020Jan 2022

Pune Institute of Computer Technology

Bachelor of Engineering

Jan 2015Jan 2019

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