Varuni Agrawal

Co-Founder

Irvine, California, United States4 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Achieved a 3.9 GPA and Dean's Honors List recognition.
Designed and verified UART IP for Bluetooth applications.
Developed optimization scripts enhancing design performance.

Stackforce AI infers this person is a Digital Design Engineer with experience in EDA and embedded systems.

Contact

Skills

Core Skills

EngineeringComputer ScienceDigital DesignHardware VerificationEdaOptimizationEmbedded Systems

Other Skills

SystemVerilogUART IP designCadence XceliumSynopsys VerdiPythonTCLFusion CompilerAI acceleratorsArduino IDEArduinoJavaCoding ExperiencePython (Programming Language)Neural NetworksArtificial Intelligence (AI)

About

Senior at the University of California Irvine with a major in Computer Science and Engineering.

Experience

4 yrs

Total Experience

2 yrs 7 mos

Average Tenure

3 yrs 9 mos

Current Experience

Infineon technologies

Digital Design Engineer

Jun 2025 – Sep 2025 · 3 mos · Irvine, California, United States · On-site

Designed and verified complete UART IP for Bluetooth team in SystemVerilog, including modular RTL design for datapath, control FSM, and background logic. I designed and simulated transmit/receive logic, baud rate generator, and control signals adhering to serial communication protocols. Utilized Cadence Xcelium and Synopsys Verdi for simulation, waveform debugging, and verification of hardware modules.
Collaborated with hardware engineers and gained hands-on experience in ASIC workflow, to validate functionality, ensuring design compliance and performance efficiency. Developed Python automation scripts to streamline design verification and naming rule conformance for internal SystemVerilog tools.

SystemVerilogUART IP designCadence XceliumSynopsys VerdiPythonDigital Design+1

Synopsys inc

Technical Engineering

Jun 2024 – Aug 2024 · 2 mos · Sunnyvale, California, United States · On-site

Developed a buffering efficiency model using TCL, optimizing design performance
within the Fusion Compiler.
Conducted a comprehensive analysis of buffer utilization and performance metrics to
identify and resolve inefficiencies.
Authored optimization scripts to enhance model functionality and efficiency.
Presented research on AI accelerators to a market leading Synopsys client, including
comparative analysis of different vendors; demonstrating strong technical and
communication skills.

TCLFusion CompilerAI acceleratorsEDAOptimization

Uc irvine

Undergraduate Student

Sep 2022 – Present · 3 yrs 9 mos · Irvine, California, United States · On-site

Current GPA: 3.9
Dean's Honors List

EngineeringComputer Science

Society of women engineers

Member

Sep 2022 – Present · 3 yrs 9 mos · Irvine, California, United States · On-site

Belakoo trust

Intern

Jun 2021 – Sep 2021 · 3 mos · Bengaluru, Karnataka, India · On-site

Belakoo trust helps promote education among disadvantaged children in rural and urban India to supplement their government school education. I lead the team in using Arduino to make a sensor-based 'polling' system to know how many times the door opened or closed in the micro-library, for this project I came up with a design to use an industrial-grade push button switch as a sensor.
The sensor has now been installed in 20 free-for-all micro-libraries at 20 hot spots across Bangalore city.

Arduino IDEArduinoEmbedded Systems