Muzammil Pasha — Co-Founder
I am an M.Tech student in VLSI Design at Amrita University, with a strong foundation in RTL design, processor architecture, and functional verification, and a passion for building efficient, scalable silicon solutions. I completed my B.Tech in Electronics and Communication Engineering from Cambridge Institute of Technology, where I developed a fully synthesizable 32-bit RISC-V processor as my final-year project, focusing on power, area, and performance optimization. This project strengthened my expertise in micro-architecture design, datapath development, pipelining, and hazard handling. Currently, my academic and research work centers on RISC-V design and verification, advanced VLSI architectures, and approximate arithmetic units for performance- and energy-efficient applications. I have strong hands-on experience in RTL design and verification using SystemVerilog and UVM, with projects involving processor verification and architectural exploration. My technical experience also includes on-chip communication protocol design and verification, such as SPI, UART, and I2C, implemented with master-slave architectures for reliable data transfer. I bring practical exposure to EDA tools including Cadence Virtuoso, Genus, Innovus, and Xilinx Vivado, along with proficiency in C, Python, and Verilog. Beyond academics, I have gained industry exposure through internships at HAL, working on electrical looms for advanced helicopters, and through the Intel FPGA Academic Program, where I designed and trained others on FPGA-based systems. I have also led sustainability-driven projects such as Smart Energy Floors using piezoelectric energy harvesting and a Smart Home Security System with GSM-based alerts. I am actively seeking opportunities in VLSI Design, RTL Design, and Functional Verification, where I can apply my skills to solve complex engineering challenges and contribute to next-generation semiconductor products. IEEE Involvement ------------------- An active IEEE volunteer for over 4 years, serving in leadership roles with IEEE Young Professionals and CEDA, and contributing to flagship technical events and professional development initiatives under the IEEE Bangalore Section.
Stackforce AI infers this person is a VLSI Design and Verification specialist with a focus on RISC-V architecture.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 3 mos
Skills
- Digital Circuit Design
- Field-programmable Gate Arrays (fpga)
- Electrical Design
- Electronics
Career Highlights
- Developed a fully synthesizable 32-bit RISC-V processor.
- Hands-on experience in RTL design and verification.
- Active IEEE volunteer with leadership roles.
Work Experience
IEEE Bangalore Young Professionals
Secretary (1 yr 2 mos)
Executive Committee Member (11 mos)
IEEE CEDA Bangalore Chapter
Executive Committee Member (8 mos)
Cambridge IEEE Student Branch
Chief Advisor & Past Chair (9 mos)
Chairperson (1 yr 1 mo)
Hindustan Aeronautics Limited
Student Intern (1 mo)
IEEE BANGALORE SECTION
Core Design Team Member- IEEE Students Activities Committee (1 yr)
Cambridge Institute of Technology
Student Representative - Intel FPGA University Program (1 yr 4 mos)
APSIS Solutions
Project Intern (1 mo)
Education
Bachelor of Engineering - BE at Cambridge Institute of Technology
