Harshit Pratik — Product Manager

Highly Experienced EDA Professional | Principal Product Engineer at Cadence Design Systems | IR/EM Expert | EDA Specialist With a strong background in electronic design automation (EDA), I excel in power integrity, electromigration, and IR drop analysis for cutting-edge semiconductor designs. Currently, at Cadence Design Systems, I leverage my expertise to support customers in utilizing the industry-leading Cadence Voltus solution for comprehensive power integrity analysis. My key responsibilities include resolving complex design challenges, deploying innovative features such as Voltus XM and Voltus Insight Flows, and empowering optimized design flows for sign-off. Prior to my current role, I served as a Senior Application Engineer at Ansys, where I supported RedHawk-SC, the industry-standard for IR drop and electromigration sign-off. I also worked as an ASIC Reliability Verification Engineer at Intel, driving EDA tool qualification and certification for Intel's process nodes. I hold a Master's degree in VLSI & Embedded Systems from Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT). My professional endeavors are fueled by a passion for EDA innovation, IC design reliability, and the creation of efficient design methodologies. Let's collaborate and share knowledge on the latest advancements in EDA, power integrity, and semiconductor reliability!

Stackforce AI infers this person is a semiconductor EDA expert with a focus on power integrity and reliability.

Location: Noida, Uttar Pradesh, India

Experience: 9 yrs 11 mos

Skills

Ir/em Analysis
Customer Enablement
Customer Support
Eda Tool Qualification
Embedded Systems
Teaching & Mentoring

Career Highlights

Expert in power integrity and electromigration analysis.
Led deployment of advanced EDA tools at Cadence.
Strong background in semiconductor design methodologies.

Work Experience

Cadence

Principal Product Engineer (5 mos)

Lead Product Engineer (1 yr 11 mos)

Ansys

Senior Application Engineer (2 yrs)

Intel Corporation

Component Design Engineer (1 yr 1 mo)

Contingent Worker (1 yr 3 mos)

Sankalp Semiconductor

Design Engineer (2 yrs 9 mos)

Dhirubhai Ambani Institute of Information and Communication Technology

Teaching Assistant (1 yr 9 mos)

Education

Master’s Degree at Dhirubhai Ambani University

Bachelor’s Degree at Swami Parmanand College of Engineering and Technology

12th Grade at St. Xavier's Higher Secondary School, Bettiah, Bihar

10th Grade at St. Xavier's Higher Secondary School, Bettiah, Bihar

Harshit Pratik

Product Manager

Noida, Uttar Pradesh, India9 yrs 11 mos experience

Key Highlights

Expert in power integrity and electromigration analysis.
Led deployment of advanced EDA tools at Cadence.
Strong background in semiconductor design methodologies.

Stackforce AI infers this person is a semiconductor EDA expert with a focus on power integrity and reliability.

Contact

Skills

Core Skills

Ir/em AnalysisCustomer EnablementCustomer SupportEda Tool QualificationEmbedded SystemsTeaching & Mentoring

Other Skills

Power IntegritySignal IntegrityEMIRFlow OptimizationVoltus InsightVoltus XMPhysical DesignPhysical VerificationVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)VerilogVHDLPerlMatlabLinux

About

Experience

9 yrs 11 mos

Total Experience

Average Tenure

Current Experience

Cadence

2 roles

Principal Product Engineer

Promoted

Jan 2026 – Present · 5 mos · Noida · On-site

Lead Product Engineer

Jan 2024 – Dec 2025 · 1 yr 11 mos · Noida · On-site

Support customers using Cadence Voltus, a leading full-chip power integrity solution, ensuring successful deployment and sign-off for advanced semiconductor designs.
Key Responsibilities:
Provide technical support for power integrity, electromigration, and IR drop analysis.
Solve complex design issues and guide customers on best practices.
Deploying advanced features like Voltus XM and Voltus Insight Flows.
Maintain recommended flows for various analysis types.
Conduct evaluations for new customers and enable optimized methodologies.
Collaborate with R&D and application engineers to resolve issues and drive tool improvements.
Core Skills: IR/EM Analysis, Voltus XM Flow, Voltus Insight Flow, Customer Enablement, Problem-Solving.

Power IntegritySignal IntegrityIR/EM AnalysisCustomer Enablement

Ansys

Senior Application Engineer

Jan 2022 – Jan 2024 · 2 yrs · Bengaluru · Hybrid

Supported customers using RedHawk-SC, the industry-standard solution for IR drop and electromigration sign-off, across advanced technology nodes.
Key Responsibilities:
Delivered technical support and deployment assistance for RedHawk-SC flows.
Guided customers on IR drop and electromigration analysis methodologies.
Worked closely with R&D to troubleshoot issues and validate new tool enhancements.
Enabled efficient sign-off flows and improved customer productivity.
Core Skills: IR/EM Analysis, Customer Support, Flow Optimization.

EMIRCustomer SupportIR/EM Analysis

Intel corporation

2 roles

Component Design Engineer

Promoted

Nov 2020 – Dec 2021 · 1 yr 1 mo

Responsible for qualifying and certifying EDA tools on Intel process nodes.
Key Responsibilities:
Drove EDA tool qualification and certification across multiple Intel technology nodes.
Performed IR drop and electromigration analysis to validate design integrity on Intel technology nodes.
Collaborated with internal design teams and EDA vendors to resolve tool limitations.
Developed and maintained IR/EM Flow to ensure robust reliability sign-off.
Core Skills: IR/EM Analysis, EDA Tool Qualification, Process Node Certification.
Tools: Cadence Voltus, Ansys RedHawk-SC, Ansys RedHawk.

IR/EM AnalysisEDA Tool Qualification

Contingent Worker

Jul 2019 – Oct 2020 · 1 yr 3 mos

Sankalp semiconductor

Design Engineer

Jan 2018 – Oct 2020 · 2 yrs 9 mos · Greater Bengaluru Area

Worked on the complete Physical Design flow for different projects under Sankalp and additionally served as a contingent engineer for Intel, focusing on EDA tool qualification and reliability verification.
Key Responsibilities:
Executed floor planning and place-and-route (PnR) using Cadence Encounter, Cadence Innovus, and Synopsys ICC/ICCII.
Performed Static Timing Analysis (STA) and timing closure using Synopsys PrimeTime.
Conducted Physical Verification (DRC/LVS) with IC Validator and Calibre to ensure design rule compliance.
Supported Power Integrity analysis using Cadence Voltus, Ansys RedHawk, and RedHawk-SC for IR drop and electromigration sign-off.
For Intel: Drove EDA tool qualification and certification for reliability verification on Intel process nodes.
Collaborated with Intel design teams and EDA vendors to resolve tool limitations and improve methodologies.
Core Skills: Floor Planning, PnR, STA, Physical Verification, IR/EM Analysis, EDA Tool Qualification.
Tools: Encounter, Innovus, ICC/ICCII, PrimeTime, IC Validator, Calibre, Voltus, RedHawk, RedHawk-SC.

Dhirubhai ambani institute of information and communication technology

Teaching Assistant

Aug 2015 – May 2017 · 1 yr 9 mos · Gandhinagar

Assisted in delivering hands-on lab sessions and supporting students in understanding embedded systems and analog circuit design concepts.
Key Responsibilities:
Embedded Hardware Design (Summer): Guided B.Tech 3rd-year students in lab practicals on ARM Assembly Language using Keil software, and worked with platforms such as Arduino Uno, BeagleBone Black, and Raspberry Pi.
Analog Circuits (Winter): Supported B.Tech 2nd-year students in simulation and analysis of analog circuits using LTSpice, followed by hardware implementation.
Provided one-on-one assistance, clarified technical concepts, and ensured smooth execution of lab exercises.
Core Skills: Embedded Systems, ARM Assembly, Circuit Simulation, Hardware Prototyping, Teaching & Mentoring.

Embedded SystemsTeaching & Mentoring