Ashutosh Kumar

Software Engineer

Bengaluru, Karnataka, India2 yrs 7 mos experience

Highly Stable

Key Highlights

Impact award for STA contribution in project.
Presented paper on power in Boston, USA.
Automated Power DV flow for SoC design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in digital architecture and low-power design.

Contact

Skills

Core Skills

Digital Ic DesignDesign IntegrationStaLow-power Design

Other Skills

CDCUnified Power Format (UPF)PerlPython (Programming Language)LINTD2DCPFSystem Verilog AssertionDebuggingAMBAUniversal Verification Methodology (UVM)SystemVerilogShell ScriptingUnixVerilog

About

I'm a chip design engineer at a leading semiconductor company, deeply fascinated by digital architecture. I feel incredibly fortunate to collaborate with and learn from some of the brightest minds in the industry. While I'm grateful for the journey so far, I’m highly ambitious about pushing the limits of what silicon can do. I’d love to connect, share ideas, and explore new opportunities. 𝗟𝗲𝘁'𝘀 𝘀𝗵𝗮𝗽𝗲 𝘁𝗵𝗲 𝗳𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗲𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰𝘀 𝘁𝗼𝗴𝗲𝘁𝗵𝗲𝗿!

Experience

2 yrs 7 mos

Total Experience

2 yrs 7 mos

Average Tenure

2 yrs 7 mos

Current Experience

Analog devices

3 roles

Digital Design Engineer

May 2026 – Present · 1 mo · Hybrid

Digital IC DesignSTA

Associate Digital Design Engineer

May 2024 – Apr 2026 · 1 yr 11 mos · Hybrid

Involved in integration of IPs in the SoC.
DV support for digital IPs
Did Joules power estimation at RTL.
worked on LINT/CDC/RDC at subsystem and SoC level.
worked on frontend STA to constraint cleanup
have STA experience on 5 nm low power chip
🏆 Impact award for my contribution for STA in project
🏆 Presented paper on power in Boston,USA.

Design integrationCDC

Digital Design Consultant

Sep 2023 – Apr 2024 · 7 mos · Hybrid

Worked on Low Power DV and Conformal Low Power Checks.
Worked on creation of UPF and low power setup for design and testbench of SoC from scratch.
Power DV- Power Number Calculation using Tempus and Voltus on GLS for peak activity test of every block of SoC.
Creation of power Tests and power window analysis.
Complete automation of Power DV Flow.
Debugging of Core Testcases.

Low-power DesignUnified Power Format (UPF)

Cadence design systems

Product Validation Intern

Aug 2023 – Aug 2023 · 0 mo · Noida, Uttar Pradesh, India · Hybrid

• Worked on Validation of OrCAD Schematic Tool - tested Part types, Part graphics, Pin package Props, Symbol Graphics, Pin operation etc.

Stmicroelectronics

SoC Verification Intern

Feb 2023 – Jul 2023 · 5 mos · Noida, Uttar Pradesh, India · On-site

Key Responsibilities & Achievements:
Verified and reviewed SoC IPs like WWDG and IWDG.
Led VCS bring-up and optimized SoC testbench size for better performance.
Automated test execution with run_test and run_formal wrappers.
Developed scripts for vPlan generation (create_vplan), warning cleanup, disk alerts, register mapping, and RTL debugging.
Played a key role in testbench enhancement and scripting infrastructure.
Awards:
🏆 Hi-Five Award for enabling run_test automation.
🏆 Hi-Five Award for contributions to testbench enhancement.

PerlPython (Programming Language)