Anil Ingale

Product Engineer

Bengaluru, Karnataka, India3 yrs 9 mos experience

Key Highlights

  • Expert in DFT with hands-on experience in multiple semiconductor projects.
  • Strong analytical skills with a focus on test coverage and debugging.
  • Proficient in leading EDA tools for ASIC design and verification.
Stackforce AI infers this person is a Semiconductor Engineering specialist with a focus on DFT and ASIC design.

Contact

Skills

Core Skills

DftEdaAsic

Other Skills

ATPG Pattern GenerationDebuggingGLS SimulationCoverage AnalysisScan IntegrationEDA ToolsDFT FundamentalsASIC Design FlowScan OperationsTessent FastscanShell ScriptingTest Coverage AnalysisASIC DesignJNVDigital Logic

About

As a DFT Engineer for intel - TechMahindra Cerium, I work with various and multiple clients, such as intel, NXP Semiconductor, Renesas Electronics, and Analog Inference, on projects of varying technology nodes having GPIS Application and Artificial Intelligence. I handle responsibilities such as ATPG pattern generation and debugging, timing and no timing GLS simulation w/wo SDF corners, coverage analysis and debug, scan integration and stitching, and working on pre-PnR and post-PnR patterns. I am proficient in different EDA tools, such as Mentor Tessent ATPG tools, Cadence Xcelium, Cadence Genus, Xilinx ISE and Xilinx Vivado, Modelsim and PSpice. I have a strong background in VLSI Design and Embedded System, having completed my MTech from premier institute Defense Institute of Advanced Technology (DIAT) in 2021. During my masters, I worked as a DFT project trainee and university project intern at NXP Semiconductor, where I gained hands-on experience in DFT fundamentals, understanding, and implementation. I learned about ASIC design flow, DFT basics, scan operations, DFT flow, Tessent Fastscan, test compression methodology, and wrote scripts and thesis on relevant topics. I also have a diploma and an engineer's degree in electronics and telecommunication engineering, and a skilled course in Embedded and VLSI. I have won multiple honors and certifications in microcontroller programming, state-level MSBTE project, signals and systems, and ASIC bootcamp. I am passionate about exploring and learning more in the DFT domain, and I have a good understanding of simulation, synthesis, STA, LEC, RTL and gates verification and simulation, HDL, and digital logic design. I am also familiar with SSA and TDF fault models, low fault coverage analysis, ATPG checks, DFT aware placement and routing, chain, serial, and parallel simulation, pattern mismatches debugging, scan chain insertion, pre-DFT and post-DFT DRCs, MBIST, and IEEE 1149.1 standard. I have strong analytical and problem-solving skills, good written and oral communication skills, and the curiosity to work on rare challenges. I am seeking DFT opportunities in the ASIC-VLSI domain, where I can apply my skills and knowledge, and contribute to the success of the organization and the industry. Happy to Respond! Reach out - 942-00-00-069 or anilingale1111@gmail.com

Experience

3 yrs 9 mos
Total Experience
1 yr 9 mos
Average Tenure
--
Current Experience

Tech mahindra

Design Engineer

Oct 2023May 2025 · 1 yr 7 mos · Cerium System · On-site

Intel corporation

Consultant

Oct 2023May 2025 · 1 yr 7 mos · On-site

Hcl technologies

DFT Design Engineer

Aug 2021Oct 2023 · 2 yrs 2 mos · Bengaluru, Karnataka, India · Remote

  • Worked with various and multiple clients - NXP Semiconductor, Renesas Electronics, Analog Inference and Much more Projects
  • Handling Responsbilities
  • ATPG Pattern Generation and Debugging
  • Timing and No timing GLS Simulation
  • SDF corners
  • Coverage Analysis and Debug
  • Scan integration and stitching
  • worked on pre PnR and post PnR patterns
  • EDA tools
  • Loving and Exploring more in #DFT
ATPG Pattern GenerationDebuggingGLS SimulationCoverage AnalysisScan IntegrationEDA Tools+2

Nxp semiconductors

Project Trainee / University Project INTERN (DFT)

Aug 2020Jun 2021 · 10 mos · Noida · Remote

  • Roles:
  • DFT Fundamentals understanding and implementation
  • 1. Understanding ASIC Design Flow.
  • 2. Understanding DFT Basics, Scan Operations, and DFT Flow.
  • 3. Understanding Tool used for DFT operations.
  • 4. Understanding the Tessent Fastscan.
  • 5. Writing scripts and performing ATPG (SAF) for Top-Level using Mentor Graphics Tessent tool.
  • 6. Understanding the Scan Insertion Flow and write scripts to implement it on the Cadence Genus tool.
  • 7. Writing Shell Scripting to easier the tasks in the flow.
  • 8. Understanding the Test Compression Methodology and its Advantages and Disadvantages.
  • 9. Writing Thesis for M.Tech. Final Year Project on 'Test Coverage Drop Analysis on Pre-Layout vs. Post-Layout Scan Inserted Netlist in SoC VLSI Design'. It includes researching new methodologies for reducing Coverage difference of Pre and Post Layout Scan inserted Netlist and implementing the Test Point insertion and providing DFT aware PnR design.
DFT FundamentalsASIC Design FlowScan OperationsTessent FastscanShell ScriptingDFT+1

Education

Defence Institute of Advanced Technology (DIAT), DU, DRDO

Master of Technology - MTech — VLSI Design and Embedded system

Jan 2019Jan 2021

Yeshwantrao Chavan College of Engineering - YCCE

Engineer’s Degree — Electronics and Tele-communication Engineering

Jan 2014Jul 2018

Indo-German Tool Room

skilled course

Jan 2014Jan 2014

S.E.S. Polytechnic Solapur

Diploma — Engineering

Jan 2011Jan 2014

Vinayak hari paranjape vidya mandir, Mahad

High School — SSC (Xth Std)

Jan 2008Jan 2011

Jawahar Navodaya Vidyalaya - JNV

2011 — JNV Tuljapur (Dharashiv)

Jan 2006Jan 2008

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