Vivek Kumar Singh — CEO
Currently working as Lead Application engineer, AMS at Cadence, Before I worked as Analog design and methodology Engineer (TFM & SUPPORT) in Intel for ~3 year and prior to this LAB Engineer (CAD Tools flow, methodology, RTL to GDS-II and AMS) at National Institute of Technology, Agartala under “SMDP-C2SD” project, sponsored by MeitY, Govt. of India. Pursuing PhD. "Some strategies to reduce power during design, synthesis and testing of VLSI circuits". Done M.Tech in VLSI Design from National Institute of Technology Agartala. Having a very good number of publications in reputed SCI and Scopus indexed journals, International conferences.
Stackforce AI infers this person is a VLSI Design expert with a focus on Analog Circuit Design and Optimization in the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 11 mos
Skills
- Application-specific Integrated Circuits (asic)
- Optimization Techniques
- Analog Circuit Design
Career Highlights
- Lead Application Engineer with extensive VLSI experience
- Strong background in Analog Circuit Design and Optimization Techniques
- Published multiple papers in reputed journals and conferences
Work Experience
Cadence
Lead Application Engineer (1 yr)
Intel Corporation
Analog Design and Methodology Engineer (1 yr 5 mos)
Cad Engineer (1 yr 3 mos)
National Institute of Technology Agartala
Lab engineer (TFM, and support) (3 yrs 3 mos)
Education
M.TECH at National Institute of Technology Agartala
Doctor of Philosophy - PhD at National Institute of Technology Agartala
Bachelor of Technology - BTech at Dr. B.C. Roy Engineering College
12th at Jawahar Navodaya Vidyalaya (JNV) Vaishali
