Harpreet Kaur — DevOps Engineer
Senior Physical Design & Synthesis Engineer with 3+ years of experience in RTL-to-GDSII flows, timing closure, and PPA optimisation. Skilled in synthesis STA, and congestion analysis using industry-leading EDA tools like Fusion Compiler, Design Compiler, ICC2, and PrimeTime. Passionate about enabling robust, power-efficient SoC designs through innovative methodologies.
Stackforce AI infers this person is a Semiconductor professional with expertise in physical design and synthesis engineering.
Experience: 4 yrs 9 mos
Skills
- Ppa Optimisation
- Timing Closure
- Digital Logic
- Embedded Systems
Career Highlights
- Expert in RTL-to-GDSII flows and timing closure.
- Improved design evaluation efficiency by 25% through innovative methodologies.
- Passionate about power-efficient SoC designs.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Senior Member of Technical Staff (1 mo)
Synopsys Inc
R&D Engineering, Sr Engineer (2 yrs 10 mos)
Post Graduate Engineer Trainee (11 mos)
Punjab Engineering College
Teaching Assistant (1 yr 11 mos)
Hewlett Packard Enterprise
Summer Trainee (1 mo)
Punjab Communication Limited
Summer Trainee (1 mo)
Education
Master of Technology - MTech at Punjab Engineering College