Harpreet Kaur

DevOps Engineer

India4 yrs 9 mos experience

Key Highlights

  • Expert in RTL-to-GDSII flows and timing closure.
  • Improved design evaluation efficiency by 25% through innovative methodologies.
  • Passionate about power-efficient SoC designs.
Stackforce AI infers this person is a Semiconductor professional with expertise in physical design and synthesis engineering.

Contact

Skills

Core Skills

Ppa OptimisationTiming ClosureDigital LogicEmbedded Systems

Other Skills

Product SpecificationSynopsys PrimetimeTimingVery-Large-Scale Integration (VLSI)VerilogRTL DesignEmbedded CProduct CertificationReal-Time Operating Systems (RTOS)RTL CodingClock Tree SynthesisFloorplanningRTL to GDSIIProject PlanningWritten Communication

About

Senior Physical Design & Synthesis Engineer with 3+ years of experience in RTL-to-GDSII flows, timing closure, and PPA optimisation. Skilled in synthesis STA, and congestion analysis using industry-leading EDA tools like Fusion Compiler, Design Compiler, ICC2, and PrimeTime. Passionate about enabling robust, power-efficient SoC designs through innovative methodologies.

Experience

4 yrs 9 mos
Total Experience
2 yrs 4 mos
Average Tenure
1 mo
Current Experience

Siemens eda (siemens digital industries software)

Senior Member of Technical Staff

May 2026Present · 1 mo · Hybrid

Synopsys inc

2 roles

R&D Engineering, Sr Engineer

Jul 2023May 2026 · 2 yrs 10 mos

  • Automation Frameworks: Architected and deployed a DTCO/PPA dashboard for Samsung Foundry; reduced analysis time by 30–40% and improved design evaluation efficiency by 25%.
  • Built workflows for timing-critical path identification and cut manual effort by 50% using predictive analytics and QoR summaries.
  • Built an automated FC–PT timing correlation workflow, accelerating debugging and strengthening timing sign-off reliability.
  • Improved client satisfaction by 30% by resolving critical multi-bit design issues in Design Compiler and Formality.
  • Investigated and closed 30+ technical cases, collaborating with R&D for complex problem resolution and enabling successful migrations.
Product SpecificationSynopsys PrimetimePPA optimisationTiming closure

Post Graduate Engineer Trainee

Aug 2022Jul 2023 · 11 mos

  • Automated PPA: Contributed in creating Python apps which lessened analysis time 90%
  • Data Collaboration: Led analytics adoption, enhancing data sharing among different teams using a centralized server mechanism.
  • Tool Reliability: Found 20+ bugs, improving stability.
  • Research work for Maters Thesis - Optimized physical design for timing precision and power efficiency, demonstrating power reduction and timing improvements
TimingVery-Large-Scale Integration (VLSI)PPA optimisationTiming closure

Punjab engineering college

Teaching Assistant

Sep 2021Aug 2023 · 1 yr 11 mos · On-site

  • Supported Analog and Digital Design labs for B.Tech students, providing hands-on guidance in circuit design and simulation.
  • Key Contributions:
  • Delivered tool knowledge sessions on Cadence Virtuoso for analog design and Xilinx ISE for digital design projects.
  • Assisted students in implementing and debugging designs such as operational amplifiers, traffic light controllers, and vending machine systems.
  • Created and evaluated assignments and lab exercises, ensuring alignment with course objectives and industry practices.
VerilogRTL DesignDigital LogicEmbedded Systems

Hewlett packard enterprise

Summer Trainee

Jun 2017Jul 2017 · 1 mo · Chandigarh, India · On-site

  • Projects - Home security system on 8051
  • Designed and implemented a home security system based on the 8051 microcontroller, integrating sensors and alert mechanisms for real-time intrusion detection.
  • Key Features:
  • Utilized IR sensors for motion detection and relay control for door locking.
  • Programmed in Embedded C for efficient control logic and interrupt handling.
  • Integrated alarm system and LCD display for status monitoring.
  • Developed a cost-effective prototype suitable for residential security applications.
  • Impact: Delivered a reliable, low-power solution demonstrating expertise in microcontroller programming, embedded systems design, and hardware-software integration.
Embedded CProduct CertificationEmbedded SystemsDigital Logic

Punjab communication limited

Summer Trainee

Jun 2016Jul 2016 · 1 mo · Mohali district, Punjab, India · On-site

Real-Time Operating Systems (RTOS)

Education

Punjab Engineering College

Master of Technology - MTech — VLSI

Aug 2021Jul 2023

Stackforce found 100+ more professionals with Ppa Optimisation & Timing Closure

Explore similar profiles based on matching skills and experience