Paul Mathews

Product Engineer

Bengaluru, Karnataka, India12 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in ASIC implementation across advanced technology nodes.
Proficient in physical design flow and timing closure.
Strong background in VLSI and digital electronics education.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC implementation and timing closure.

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Skills

Core Skills

Physical DesignStatic Timing AnalysisVery-large-scale IntegrationClock Tree Synthesis

Other Skills

Import DesignFloorplanningPlacementRoutingCongestion OptimizationECO ImplementationTcl ScriptingPorts & Macro PlacementPower PlanningDRC ViolationsHardware DesignVLSIElectronic Circuit DesignMicrosoft WordMicrosoft Office

About

Physical Design Engineer with 2 years of hands-on experience in ASIC implementation and timing closure across advanced technology nodes (7nm, 16nm, 28nm). Skilled in end-to-end physical design flow including floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, and Static Timing Analysis (STA). Experienced in resolving setup/hold violations, congestion optimization, and improving QoR through timing-driven techniques. Proficient in PrimeTime for STA (setup/hold analysis, skew, insertion delay) and Innovus for implementation. Worked on block-level designs up to ~1.3M instances and high-frequency targets, ensuring design closure. Strong understanding of SDC constraints, parasitic effects, and variation-aware timing (OCV/AOCV). Hands-on experience in ECO implementation (DMSA and manual), DRV fixing (max transition/capacitance), and post-route DRC closure. Also experienced in Tcl scripting for PD automation and report analysis. Previously worked as an Assistant Professor in Electronics and Communication Engineering, building strong fundamentals in Digital Electronics, VLSI, and problem-solving. This background supports effective debugging, analysis, and collaboration in complex design environments.

Experience

12 yrs 7 mos

Total Experience

10 yrs 7 mos

Average Tenure

2 yrs

Current Experience

Blueberry semiconductors

ASIC Physical Design Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Physical Design Engineer working on block-level ASIC implementation and timing closure for advanced-node SoC designs (7nm/16nm/28nm).
Experienced in end-to-end physical design flow: floorplanning, placement, CTS, routing, and timing closure.
Hands-on experience in STA using PrimeTime, including setup/hold analysis, skew, and insertion delay optimization.
Worked on high-complexity designs (up to 1.3M instances, 800+ MHz) ensuring QoR targets.
Performed congestion analysis and applied optimization techniques like blockages, halos, and cell padding.
Implemented ECOs for timing closure using tool-based (DMSA) and manual fixes.
Resolved DRVs (max transition, max capacitance) and post-route DRC violations.
Applied timing-driven placement and datapath optimization to improve critical path performance.
Experience with SDC constraints, OCV/AOCV concepts, and variation-aware timing analysis.
Automated PD tasks using Tcl scripting for report analysis and flow improvements.

Physical DesignImport DesignFloorplanningPlacementClock Tree SynthesisRouting+4

Takshila institute of vlsi technologies

Physical Design Engineer

Aug 2023 – Mar 2024 · 7 mos · Bengaluru, Karnataka, India · Remote

Worked on ASIC Physical Design training project (ORCA_TOP_IO) using Synopsys IC Compiler II (28nm).
Executed floorplanning and macro/IO placement for ~50K instance design with 30 macros.
Implemented power planning and defined power grid for reliable routing.
Applied placement optimization techniques to reduce congestion and improve routability.
Performed Clock Tree Synthesis (CTS) for multi-clock design (7 clocks).
Carried out routing across 9 metal layers and resolved DRC violations.
Contributed to achieving design closure at 400 MHz with improved QoR.

Ports & Macro PlacementVery-Large-Scale IntegrationPower PlanningClock Tree SynthesisRoutingDRC Violations