NANDINI CHALLA — Product Engineer
✓My focus lies on Synthesis, PNR and PV . ✓handled physical implementation of a PD block, working on floorplan includes macro/IP placement, powerplan and estimation of utilisation . ✓Performed Placement CTS and signal routing using industry standard tools (FC and innovus). ✓I performed DRC LVS cleaning for PV closure. ✓Ran STA with prime timing to fix timing DRV violations across MCMM corners. ✓Collaborating in project team to understand debug congestion, timing violations, physical DRCs. ✓I explored ECO flow to understand the implementation cycle.
Stackforce AI infers this person is a Physical Design Engineer with expertise in ASIC development and implementation.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 10 mos
Skills
- Physical Design
- Floorplanning
- Low-power Design
Career Highlights
- Expert in Physical Design and Low-power Design.
- Proficient in DRC LVS cleaning and timing closure.
- Hands-on experience with industry-standard tools.
Work Experience
Samsung R&D Institute India
Assistant SOC PI/PD Engineer in SSIR (Direct-Contract) (1 yr 10 mos)
SOCDV Technologies Private Limited
Physical Design Engineer (1 yr)
Education
Student at JNTUA college of engineering at JNTU Anantapur
MPC at Sir CV Raman junior college
