Parthasarathy G — Director of Engineering

o Expertise in SOC validation, Emulation on Palladium and Zebu platforms, Creating Emulation setup from simulation database, mapping FPGA libraries, bring up of Emulation flow , IP/SOC verification regressions and debugging, o Expertise in FPGA Prototyping methodologies, design partitioning of SOC into multiple FPGAs , constraints generation, physical synthesis, place and route, FPGA-RTL simulation, and Debug , Validation on HAPS80/70 systems , custom FPGA boards, Board bring-up, Firmware stitching, execute the SW driver tests and system validation o System integration, Test bench and Test plan creation for subsystem and verification o Strong expertise in FPGA Timing closure o Expertise in module level, and chip level verification using Verilog, C, Good knowledge in HVL Specman and System Verilog UVM. o Expertise in equivalency Checking LEC, design analysis using spyglass suit of tools for linting, constraints, CDC for FPGA o Expertise in Project lead and People Management , status updates and Delivery management, Customer interaction and support , setting the best practices and processes for the team and ensuring its compliance, o Prototyping of Customer designs on HAPS systems for evaluations, addressing tool performance issues. o Evaluations and bench marking of Synopsys Prototyping and Implementation Products. o Build validation, certification and release ownership. o Regression management, handle regression failures, add , QOR designs to Regression suit o QOR metrics analysis isolation of tool issues and performance issues, Improve QOR methodologies with new features addition o Customer support, Track, facilitate customer Bugs, Enhancements and defect report

Stackforce AI infers this person is a specialist in ASIC Emulation and FPGA Prototyping within the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs 8 mos