Atharva Chopade — Software Engineer

Highly Motivated Analog Layout Engineer 1. Proficient in floor-planning, layout design, and verification of complex clock circuits, ensuring compliance with all LV bundle verification flows. 2. Strong expertise in signal flow, clock routing, shielding, power and ground structures, and bias signal routing, with a focus on high-performance design. 3. Skilled in custom and analog layout, effectively addressing challenges related to EM/IR, shielding, and design optimization. 4. Specialized in advanced technology nodes, including FinFET (Intel 5nm, 7nm) and higher-node BiCMOS/CMOS technologies (TSMC 16nm, 28nm,45nm & 90nm), GF 130nm. 5. Experienced with industry-standard EDA tools such as Cadence Virtuoso (XL & EXL), IC Validator VUE, and Caliber for efficient design and verification. 6. Demonstrated strong debugging capabilities in physical verification checks, including LVS, DRC, ERC, and density analysis, ensuring robust and reliable designs.

Stackforce AI infers this person is a highly skilled Analog Layout Engineer specializing in advanced semiconductor technologies.

Location: Bengaluru, Karnataka, India

Experience: 2 yrs 11 mos