Gurleen Kaur Kalra

Product Manager

New York City, United States2 yrs 1 mo experience
Highly Stable

Key Highlights

  • Led assertion development for low power sequences.
  • Achieved 100% code coverage in multiple projects.
  • Recognized with Execution Excellence and Integrity Awards.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC development.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Integrated Circuits (ic)Physical DesignApplication-specific Integrated Circuits (asic)System On A Chip (soc)

Other Skills

VerilogRTL SynthesisStatic Timing AnalysisFloorplanningVLSICOMSOLAnalog CircuitsDigital DesignTCLDebuggingSystemVerilogTest PlanningRTL CodingSQLPerl

About

Career Objectives: As a Student pursuing my MS in Electrical Engineering specializing in Integrated Circuits & Systems at Columbia University, School of Engineering & Applied Sciences, I am deeply committed to advancing my academic and professional journey within the Semiconductor industry. With a strong academic & research foundation and hands-on experience in digital design, low-power verification, and advanced VLSI methodologies, I aspire to pioneer goal-driven innovations that shape the future of electronics and emerging technologies. Motivated by a passion for technological transformation, I eagerly explore cutting-edge developments in integrated circuits, SoC architecture, and next-generation semiconductor design. My academic concentration in Integrated Circuits & Systems, complemented by industry exposure and relevant certifications, enables me to continually enhance my technical expertise and stay aligned with evolving industry trends. I thrive in collaborative and dynamic environments, where creativity, problem-solving, and cross-functional teamwork drive impactful engineering outcomes. Throughout my journey, I have participated in multiple competitions, earned recognition through awards, and contributed to research projects focused on efficiency, scalability, and innovation in chip design. My long-term goal is to create meaningful technological advancements by blending rigorous engineering knowledge, innovative thinking, and a commitment to excellence—ultimately contributing to transformative semiconductor solutions that propel the electronics industry forward.

Experience

2 yrs 1 mo
Total Experience
2 yrs 1 mo
Average Tenure
--
Current Experience

National institute of electronics & information technology (nielit)

RTL-to-GDSII Design Flow Intern

Jun 2026Present · 0 mo · Gorakhpur · Remote

  • Overview of VLSI Design Flow
  • Hardware Modeling: Introduction to Verilog-I using Icarus Verilog
  • RTL Synthesis with YOSYS tool
  • Static Timing Analysis using Open STA
  • Basic Concepts for Physical Design
  • Floorplanning, Clock Tree Synthesis, Routing
  • Layout Design using Magic Tool
VerilogRTL SynthesisStatic Timing AnalysisPhysical DesignFloorplanningVery-Large-Scale Integration (VLSI)+1

Indian institute of science (iisc)

PG - Level Advanced Sensor Technology and Chip Design Research Programme

May 2025Nov 2025 · 6 mos · Bengaluru, Karnataka, India · Remote

  • Facilitator : Dr. Hardik Jeetendra Pandya
  • Curriculum:
  • Module 1: Introduction to Sensors and MEMS Sensor Fundamentals
  • Module 2: MEMS Sensor Fabrication and Characterization Techniques
  • Module 3: Sensors and Analog Circuits
  • Module 4: Numerical Simulation of Sensors and Actuators using COMSOL Multiphysics
  • Module 5: Sensor System Integration-Concepts, Tools and State-of-the-Art
  • Module 6: Ultrasound Engineering and its Applications
  • Module 7: VLSI and ASIC Design for Complex Chip Creation
  • Module 8: Foundations of Digital Design and FPGA Programming with Verilog
  • Module 9: Advanced Digital Circuit Design- CMOS, Logic Families, and Memory Systems
  • Capstone Project
VLSICOMSOLAnalog CircuitsDigital DesignVery-Large-Scale Integration (VLSI)Integrated Circuits (IC)

Maven silicon

Advanced Physical Design & Verification

Nov 2024Apr 2025 · 5 mos · Bengaluru, Karnataka, India · Remote

  • Curriculum:
  • 1) Introduction to Physical Design
  • 2) VLSI Physical Design - CMOS Devices and Technologies
  • 3) VLSI-Physical Design - Synthesis and PDKs
  • 4) VLSI-Physical Design - Physical Verification
  • 5) VLSI-Physical Design - Design for Testability (DFT)
  • 6) VLSI-Physical Design - Static Timing Analysis (PD)
  • 7) VLSI-Physical Design - Defing Timing Constraints using SDC
  • 8) Fusion Compiler Design Planning
  • 9) VLSI-Physical Design - Floorplanning
  • 10) VLSI- Physical Design - Power Plan
  • 11) VLSI-Physical Design - Placement
  • 12) VLSI-Physical Desgn - Clock Tree Synthesis
  • 13) VLSI-Physical Design - Routing
  • 14) VLSI-Physical Design - Fusion Compiler (Design Implementation) - Tool - Signoff
  • 15) Signal Integrity and Cross Talk Issues
  • 16) VLSI-Physical Design - Physical Verification
  • 17) TCL
Static Timing AnalysisSystem on a Chip (SoC)TCLPhysical DesignDebuggingVery-Large-Scale Integration (VLSI)

Isro - indian space research organization

Exploration of Solar System Training Program

Apr 2024May 2024 · 1 mo · Bengaluru, Karnataka, India · Remote

  • Completed the Exploration of the Solar System module under ISRO’s Space Science and Technology Awareness Training (START) program.
  • Gained foundational knowledge of solar system formation, planetary science, and heliophysics, including the Sun, planets, moons, and minor celestial bodies.
  • Developed an understanding of scientific objectives, mission planning considerations, and exploration strategies for interplanetary missions.
  • Attended expert lectures delivered by scientists and researchers from ISRO and associated space research institutions.
  • Acquired an interdisciplinary perspective on the integration of space science and engineering in planetary exploration missions.
  • Strengthened exposure to space science and technology concepts, relevant to advanced engineering research and space-technology applications.

Synopsys inc

ASIC Digital Design Engineer (R&D)

Jul 2022Aug 2024 · 2 yrs 1 mo · Bengaluru · On-site

  • Worked as a member of UFS Subsystem Team (Mixed Signal Intellectual Property)
  • Responsibilities:
  • 1) Assertion Development:
  • Led assertion development for Low Power and Power Up Sequences, enhancing verification efficiency for a leading semiconductor design company.
  • Orchestrated Isolation Check Assertions, ensuring system robustness and reliability for top-tier clients.
  • Recognized with the Execution Excellence Award and Integrity Award for consistently delivering high-quality results and meeting project deadlines.
  • 2) Functional Connectivity Checks:
  • Spearheaded functional connectivity checks and clock-gating procedures, validating critical system functionalities for a major semiconductor manufacturer.
  • Achieved 100% code coverage across various metrics, showcasing meticulous attention to detail and thoroughness in testing procedures.
  • Provided mentorship to junior engineers, fostering a collaborative work environment for projects with renowned semiconductor companies.
  • 3) Testcase Development:
  • Developed original system and unit level test cases for SRAM access and interrupt features, contributing to comprehensive test coverage and system reliability.
  • Played a key role in achieving 100% code coverage, ensuring thorough testing while optimizing resources effectively.
  • Served as a reference point for test case development across multiple projects, with other teams taking inspiration from the test cases I developed.
  • 4) Automation and Knowledge-Sharing:
  • Contributed to automation script development, streamlining workflows and enhancing efficiency in design processes.
  • Prepared knowledge-sharing presentations on complex subsystems, showcasing expertise in areas such as UFS Host Controller and Scatter-Gather features.
  • Maintained focus on continuous learning, gaining proficiency in emerging protocols and technologies like Mipi Unipro and Inline Encryption.
  • Participated in SNUG 2024
SystemVerilogTest PlanningRTL CodingDebuggingPhysical DesignApplication-Specific Integrated Circuits (ASIC)+1

Maven silicon

Advanced VLSI Design & Verification

Jan 2022Jul 2022 · 6 mos · India · Remote

  • A 6-month VLSI training and internship program consisting of Digital Electronics, Verilog HDL, System Verilog, UVM, STA, RISC V Processor, Business Communication, and other modules. Worked on Router 1X3 Design and Verification, AHB to APB Bridge Verification projects.
  • Top performer in Verilog HDL and System Verilog modules.

Internshala

Internet of Things

May 2020Jun 2020 · 1 mo · India · Remote

  • A four-week online training on Internet of Things. The training consisted of building an IoT Monitoring System, controlling devices over the internet, Clouds APIs & Alerts and Machine Learning with IoT modules. Scored 97% in the final exam and was a top performer during the training.
SystemVerilogVerilogDebuggingTCLVery-Large-Scale Integration (VLSI)Integrated Circuits (IC)

Manipal university jaipur

Hands-on Training for Diode Fabrication

Jul 2019Dec 2019 · 5 mos · Jaipur, Rajasthan, India · On-site

  • Fabricated diode on N-type Silicon wafer using Oxidation, Photolithography, Diffusion, Metallization, Metal Etching and Metal Contact processes, and various lab equipments and chemicals and prepared a detailed presentation.

Education

Columbia University

Master of Science - MS — Electrical Engineering

Aug 2025Dec 2026

Manipal University Jaipur

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jul 2018Jul 2022

St. Paul's Convent Sr. Sec. School, Ujjain

Class XII CBSE — PCM + IP

May 2016May 2018

St. Paul's Convent Sr. Sec. School, Ujjain

CBSE Class X

Apr 2005Apr 2016

Stackforce found 100+ more professionals with Very-large-scale Integration (vlsi) & Integrated Circuits (ic)

Explore similar profiles based on matching skills and experience