Andrew Pham

Director of Engineering

Ho Chi Minh City, Vietnam18 yrs 1 mo experience

Highly Stable

Key Highlights

Expert in full chip physical design from RTL to GDS.
Proficient in DFT and static timing analysis.
Led significant projects in semiconductor design.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in Physical Design and DFT.

Contact

Skills

Core Skills

Physical DesignDftLow Power DesignStatic Timing Analysis

Other Skills

SoC Top PD designfloorplaningpartitionctstiming closuredrc/lvs/erc/IRDFT SYNSTARTL to GDSPD tasksmultiple PD toolsSTA constraint analyzingtiming analyzingDFT whole flow chip designmultiple fuse type handling

About

Handle full chip physical design, 28nm to 7nm tsmc processes, design size around 100M instances. Experience full chip Physical Design DFT Synthesis and STA.

Experience

18 yrs 1 mo

Total Experience

4 yrs 9 mos

Average Tenure

1 yr 9 mos

Current Experience

Skyechip

Director of Engineering

Sep 2024 – Present · 1 yr 9 mos · Vietnam

Synopsys inc

BackEnd Manager

Jun 2021 – Nov 2024 · 3 yrs 5 mos · Ho Chi Minh City, Vietnam · On-site

Mediatek

2 roles

Technical Manager

Promoted

Jun 2019 – Jan 2024 · 4 yrs 7 mos · Singapore

Staff Engineer

Jan 2016 – May 2019 · 3 yrs 4 mos · Singapore

Physical Design: Handle SoC Top PD design, mobile and asic projects.(chipsize ~ 60M instances)
floorplaning - partition - cts - timing closure - drc/lvs/erc/IR.
Can also handle DFT SYN and STA.

Physical DesignSoC Top PD designfloorplaningpartitionctstiming closure+4

Esilicon

Senior Physical Design Engineer

Dec 2012 – Dec 2015 · 3 yrs · Viet Nam

Completed big projects with some keys IPs (SerDes/PCIE IP, SerDes/Ethernet IP , GPU IP…), full flow RTL to GDS,
Handle PD tasks with multiple PD tools (Talus/ICC/ICC2/Atoptech/Innovus).
Handle Low power design with multi domain inside.

RTL to GDSPD tasksLow power designmultiple PD toolsPhysical DesignLow Power Design

Renesas mobile corporation

Senior Physical Design Engineer

Mar 2008 – Dec 2012 · 4 yrs 9 mos · VietName

Layout/STA senior engineer:
STA constraint analyzing, timing analyzing and fixing, sign-off timing qualification
DFT senior engineer:
DFT whole flow chip design (scan, mbist, lbist, from cleaning netlist for DFT implement to verification)
Handle multiple fuse type (CU/LT Fuse, E-Fuse, Anti-Fuse) from implement testing and memory reparing pattern

STA constraint analyzingtiming analyzingDFT whole flow chip designmultiple fuse type handlingStatic Timing AnalysisDFT