Sung-il Kim

Software Engineer

Austin, Texas, United States22 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Power/Performance/Area optimization for advanced semiconductor nodes.
Pioneered the use of Fusion Compiler for mass production at Samsung.
Delivered high-performance ARM-based CPUs and GPUs for mobile devices.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in EDA tools and optimization techniques.

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Skills

Core Skills

Power/performance/area OptimizationFusion CompilerInnovusDfm

Other Skills

Technical supportParasitic ExtractionPlacement and routingDRCLVSESD Auto Check(EAC)ATPGStatic Timing Analysis(STA)Physical DesignPerlTCLLayout Versus Schematic (LVS)Noise AnalysisRTL designVLSI

About

Project Leader, Physical Design Engineer specialized to Power/Performance/Area optimization for High Performance AI, mobile and automotive NPU/GPU/CPU/SOC on advanced nodes of TSMC, SEC. Experiences: - Tape Outs with Full RTL2GDS Flow(Functional Simulation, Synthesis, DFT Insertion, ATPG, Formal Check, Placement, Clock Tree Synthesis, Routing, Chip Finish, Parasitic Extraction, Static Timing Analysis, IR Analysis, ECO, DRC, LVS, ESD Auto Check) - Benchmarks for Placement & Routing tools against competitors - Technical Supports for Customers

Experience

22 yrs 2 mos

Total Experience

5 yrs 6 mos

Average Tenure

7 yrs 3 mos

Current Experience

Synopsys inc

Principal Application Engineer

Mar 2019 – Present · 7 yrs 3 mos · Austin, Texas, United States

Very first application of Synopsys's new Placement and Routing tool, FusionCompiler, for mass production device in Samsung
Power/Performance/Area optimization with FusionCompiler for CPU, GPU and NPU in high end mobile or automotive SOCs on advanced nodes such as TSMC 2/3nm and Samsung 2/3nm.
Technical supports for users of FusionCompiler to help customer's successful tape-out

Fusion CompilerPower/Performance/Area optimizationTechnical support

Mentor graphics

Sr. Application Engineer Consultant

Oct 2015 – Feb 2017 · 1 yr 4 mos

Very first and successful implementation of testchip in Samsung by Menton's placement and routing tool
Tech file validation for companies using Mentor's placement and routing tool

Cadence design systems

Staff Application Engineer

Feb 2015 – Oct 2015 · 8 mos

Successful deployment of Cadence's new Placement and Route Tool, Innovus, to Samsung by showing better Power/Performance/Area with faster runtime than competitor's
Placement and Routing with Innovus with Power/Permance/Area optimization for sub blocks of SOC

InnovusPower/Performance/Area optimization

Samsung electronics

Senior Engineer

Feb 2002 – Jan 2015 · 12 yrs 11 mos

Successful deliveries of the top of the range ARM-based CPUs & GPUs for high performance mobile devices as a front & back-end engineer
Key role was Power/Performance/Area optimization to make top notch mobile devices.

DFMParasitic ExtractionPower/Performance/Area optimization