Vinayak Patil

Software Engineer

Bengaluru, Karnataka, India6 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in physical design engineering.
  • Proficient in static timing analysis and timing closure.
  • Skilled in VLSI design methodologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and timing analysis.

Contact

LinkedIn

Skills

Other Skills

Static Timing AnalysisPhysical DesignClock Tree SynthesisTiming ClosureFloorplanningVery-Large-Scale Integration (VLSI)TCLPNRcadence innovuscadence genussynthesispower planning

Experience

6 yrs 5 mos
Total Experience
2 yrs 1 mo
Average Tenure
3 yrs 3 mos
Current Experience

Synopsys inc

2 roles

Staff Physical Design Engineer

Promoted

May 2026 – Present · 1 mo

Senior Physical Design Engineer

Feb 2023 – Apr 2026 · 3 yrs 2 mos

Cerium systems

Physical Design Engineer U2

Jul 2022 – Jan 2023 · 6 mos · Banglore

Cadence design systems

3 roles

Senior Physical Design Engineer

Promoted

Jul 2021 – Jun 2022 · 11 mos

Physical Design Engineer

Sep 2019 – Jun 2021 · 1 yr 9 mos

Physical Design Engineer

Apr 2019 – Aug 2019 · 4 mos

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